2019-01-02 09:37 AM
EPENA bit for IN endpoint 0 (OTG_FS_DIEPCTL0 register) is marked as read-only both in the reference manual and in the SVD files for F429.
I believe that is a mistake, as the EPENA bit is used to start transmission on the endpoint and both libopencm3 and STM32 LL drivers ignore the fact that the bit is marked as read-only.
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) {
// other code
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
// other code
}
It's possible that the DIEPCTL0 EPENA bit was confused with the DOEPCTL0 EPENA bit, which is marked as write-only, even though it should probably be read-only.
Would someone clarify this for me?
Solved! Go to Solution.
2019-01-02 12:34 PM
> ref. manual mistake?
Yes.
These bits are not even rw, as they are set by user and cleared by hardware (DOEPCTL0 EPDIS is read-only, as EP0 Rx can't be disabled). This Synopsys OTG IP contains several such control bits which are changed by both user and hardware.
JW
2019-01-02 12:34 PM
> ref. manual mistake?
Yes.
These bits are not even rw, as they are set by user and cleared by hardware (DOEPCTL0 EPDIS is read-only, as EP0 Rx can't be disabled). This Synopsys OTG IP contains several such control bits which are changed by both user and hardware.
JW
2019-01-02 01:01 PM
Ah, makes sense, I completely forgot that bits the core controls have special access rights. Thanks for the answer.
Do you know where should I point this to get it fixed? I don't really mind that it's wrong in the reference manual, but my tooling is based upon SVD files ST provides, so I'd really like to have it fixed officially.
2019-01-04 04:53 AM
> my tooling is based upon SVD files ST provides, so I'd really like to have it fixed officially.
Unless some of the moderators chime in here - and I don't know if there is any path from here to SVD files - you might better contact ST directly through the web support form or through a FAE.
JW