2023-02-23 07:24 AM
Hello,
I apologize if this is an obvious question, but I do not want this part to be wrong and would prefer some confirmation.
I am preparing a custom board and would like to program it in an identical manner to the evaluation/nucleo boards. To try and achieve this, I would like to use the STLINK-V3SET. To minimize the space on the board, I put a 2.54mm pitch, 6 pin connector on my board that is connected to the SWD pins as shown below.
The STLINK-V3SET comes with an adapter board that has the 6-pins configured in the same order as the SWD connector on my application board.
Based on this, I have three questions:
1) Based on this setup, will there be any obvious issues programming the board?
2) If I want to program the board like I have been in previous projects on the evaluation/nucleo boards (via CubeIDE through the Run button, with the setup below), will it work if I connect to the SWD connector (CN6) on the adapter board?
3) Will the STLINK-V3SET power the MCU to program the board if I connect the 3.3V pin (Pin 1 in CN6)? Or will my application board have to be powered seperately? (I see the comment 1 in Table 11 about it being an input for STLINK-V3SET, but I'm confused on whether it means it is the input for the application board or the application board powers the STLINK-V3SET)
Solved! Go to Solution.
2023-02-23 09:26 AM
and dont forget cer. caps on nrst, boot0 , vcap -- gnd.
2023-02-23 09:26 AM
and dont forget cer. caps on nrst, boot0 , vcap -- gnd.
2023-02-23 09:52 AM
Hello AScha,
Thank you for the reply!
I appreciate you confirming my logic :)
Yes, I do have caps on NRST and VCAP. I kept the capacitors separate to reduce schematic clutter.
Would Boot0 need it too if it's always connected to GND?
2023-02-23 11:11 AM
You don't need a capactor on BOOT0, it's pulled down to assure a specific state on systems where there's a slow rise time on the power rails, and if left floating can be in an indeterminate state.
Surely the VCAP caps should be 2.2uF (pair) or 4.7uF (single), certainly for LDO implementations where the MCU generates it's own 1.25V rail.
2023-02-23 11:32 AM
Hello Tesla,
Thank you for the reply!
I currently have 1x 10uF and 2x 100nF ceramic capacitors near the output of Vcap. Is that sufficient? Or is there issues with having it larger than 4.7uF?
Note that I based my capacitor sizes off the STM32H7B3I-EVAL board (but it uses SMPS, but LDO).