DAC Exercise in STM32F4xx

[Yoshimitsu_Manji_clan]

Good evening everyone,

today I generated a sine wave (using array method, 80 samples per time period) and got it on oscilloscope using DAC channel 1. Then I tapped this analog wave into the ADC of the board. Then i again converted the data from ADC channel and got it on oscilloscope via DAC channel 2. I observed that the sine wave of channel 2 is clipped near the peak whereas channel 1 wave is perfectly fine. Then I scaled down the actual sine wave and observed that the two waves are not clipped anymore. Has someone else experienced the same problem and if yes, what is the probable cause to this issue? 

thanks and regards.  

[TDK]

The DAC is not perfectly rail to rail when the buffer is enabled. If you disable the buffer then rail to rail performance improves but the output impedance goes up significantly.

Even "rail to rail" op amps don't actually go the entire way to the rail. Typically they will stop around tens of mV from each one.

[MasterT]

Nucleo-F4?

There is a LED on pin A5, check out schematic , remove jumper if necessary