2006-05-10 01:57 AM
2006-05-08 05:20 AM
Hello,
I'm using the ST10F276's XSSC in order to implement a SPI protocol. I need to know when the transmission ends (the las bit was transmitted) but the 8th bit of XIR0SEL only notifies that the XSSCTB can be reloaded. Am i missing something? thanks in advance, Dvir2006-05-08 10:33 PM
Hello Dvir,
The 8th bit of XIR0SEL register is CAN1 interrupt enable??? I don't think that you are speaking about this bit but about the XSSC Transmit interrupt request. Is this the case? Transmit data is written into the Transmit Buffer XSSCTB. It is moved to the shift register as soon as this is empty. When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt request will be generated to indicate that XSSCTB may be reloaded again. When the programmed number of bit (2...16) has been transferred, the contents of the shift register are moved to the Receive Buffer XSSCRB and a receive interrupt request will be generated. If No further transfer is to take place (XSSCTB is empty), the hardware controlled bit SSCBSY will be cleared at the same time. I hope this answers your question. If this is not the case, could you please explain more your problem? Best regards, Najoua.2006-05-08 11:45 PM
Hello Najoua,
yes, the bit i was talking about is XSSC Transmit interrupt request (and not the 8th bit). Thanks for your answer, but this is not what I'm looking for. I'll try to explain it in more details: I'm using the XSSC to implement a SPI protocol. The SPI is used to connect between the ST10 (the master) and a serial flash (the slave). Now, lets assume i want to write to specific address in the serial flash. The serial flash demands that chip select signal will be raised to '1' after the last data bit was transmited. So i need to know when the last bit was transmitted and the XSSC Transmit interrupt request bit does not give me that information. Is there other register i can use ? Best regards, Dvir