I’m currently having an issue w/ ST Micro P/N M4T11M6 RTC w/ clock drift. Specifically, I’ve performed verification testing on 4 units to this point and I’m seeing over 8 seconds/day (Extrapolating to a value of 4.25 minutes/month) of drift from NIST time. The RTC clock calibration register only allows for a maximum of -2.75 minutes/month which isn’t enough range to allow for the drift observed to be calibrated out. This makes me question my PCA schematic and perhaps layout design. The XTAL used meets the required 32.768 KHz XTAL w/ 12.5 pF load capacitance. I have cut-away the GND plane under the XTAL as well (However, it turns-out the +3.3V plane isn’t cut-away, but is in the middle of the 8 layer stack-up and the RTC and XTAL are on the top layer).
What am I potentially doing wrong that would cause such a drift issue?
We are in the middle of verification on a high-priority project w/ a tight schedule, so your urgency on this matter is truly appreciated. Thanks in advance for your assistance w/ resolving this RTC issue.
That sure looks like the SO8 package to me.
> M4T11M6
This is an SO8 package part number.
Am I missing something? I bet the load caps are not integrated. Datasheet could be improved for clarity.
I don’t see a soic8 package in the datasheet.
No. It looks like you're correct. I made the assumption that I had a different package based off of Digikey.com information which is apparently incorrect. As you can see in the screenshot below, it's stating 8-SOIC. Maybe that's the same, but thought SO8 was different even thought I didn't exactly know how. Thanks for bringing to my attention.
Regardless, after re-reading the notes in the datasheet, I'm interpreting the first note as applying to the external crystal because Table 8 is referring to the parameters of the external XTAL to which resonant frequency, series resistance, and load capacitance applies. There's no reference to load capacitors in this statement. This just means that all of those parameters are applicable via the XTAL characteristics. Note 2 literally flat-out says the load capacitors are integrated internal to the IC w/o mentioning that the package type matters at all w/ this statement. With this, I don't think the package type even matters. There's no references in the datasheet to determine what load capacitance is needed and how to calculate. I think this just goes further to say the load capacitors are integrated and external load capacitance is NOT intended or needed to meet the datasheet PPM clock drift. Although, I'm still not sure if the 35 PPM is literally just the IC and I need to add another PPM value to account for the XTAL I'm using??? Trying to understand what the actual PPM I should expect if my XTAL is 20PPM. Anyone know if this calculation is just additive: 35 PPM from IC + 20 PPM from XTAL = 55 PPM???
So in so8 case - the load caps are "external" , you have to put them to the crystal.
Only the " snaphat " integrates the crystal + load caps ....
So without changing your design you could try what i wrote ... or try a low cap crystal,
what might match the stray capacitances .
