Dear all,
I have designed a high voltage switching circuit using a half-bridge topology which employs the SCT1000N170 SiC MOSFETS as the power switches. The aim is to apply the design as a pulsed-dc power supply for driving a magnetron sputtering gun. Two of UCC5390 single-channel Isolated gate drivers are used for driving the gate of the switches. The diving signals are generated from a microcontroller (Arduino due).
The schematic of the half-bridge part is attached as figure 1. Based on a SPICE simulation (PSpice-For-Ti), the design appears to work fine. However, when implemented onto a pcb (2-sided, conventional lead soldering of parts), there is a major problem. The pulsed-dc voltages across a resistive load exhibits a slow decay at the end of a positive pulse, and a slow build-up at the end of a negative pulse, see figure 2. The curves occur in off-time durations, i.e. when the gate drive signals of both switches are LOW. The rails HV were +- 150 VDC. Further investigation using the SPICE simulator suggests that the decaying and build-up curves are likely to be the results of the discharge and charge, respectively, of a parasitic or stary capacitances present across the drain and source terminals of the switches. The magnitude of the capacitance is about 1000-2000 pF, which is about two order-of-magnitude higher than the specified COSS of the SCT1000N170.
What are the possible sources of these apparent parasitic or stary capacitances? Advice and suggestions to eliminate them are greatly appreciated.
Kind regards,
Thanusit Burinprakhon
