Problems with PWD13F60 on my own pcb desing

[FGall]

Hi, currently in my application i am handling an inductive load without problems with the evaluation board of PWD13F60, but when I use the IC in my 2 layer PCB design it explodes when applying 310VDC, with voltages lower than 250VDC approximately it works without problems.

Could you tell me what considerations I should have in the design of PCBs, or analyze what problems do I have in the gerbers of my design?.

From already thank you.

[lauria.michele]

Hi,

Can you confirm that you experience the failures by simply applying 310V to VS pin (no load switching)?

If this is the case the issue with your PCB design might be a very short creepage distance between high-voltage and low-voltage pins of the device.

 Please keep at least 1.2 mm distance between:

VS traces and BOOT/OUT traces

Vs trace and any other LowVoltage trace

BOOT/out traces and at other Low-voltage trace

Thanks and regards

Michele Lauria

[fabbri.fabio]

Dear Francesco, have you solved your problems?

ST eval board word fine also with much higher voltage.

the 1.2mm recommended distance shall be kept between the following groups:

1) VS

2) OUT1, BOOT1

3) OUT2, BOOT2

4) all the rest.

Do the problem occur with or without load? If it occurs only with load, I would recommend to check:

1) if shunt current sense resistor is used, it is better to split it in two separate shunt resistor as it is done in the evaluatio board. Then connect  GND and and SENSE with two properly sized traces.

2) it is better to connect the bootstrap capacitor negative pin with a direct trace to the OUTx pad.

In general you could consider as 2 layer routing example the EVALPWD5F60 board, which have a similar architecture.