I'm currently investigating mechanisms for synchronization of disparate IIS3DWB units in a given system. The current thought is that signal alignment between two disparate IIS3DWB units can be achieved without a traditional SYNC signal by aligning to a common "flag" or indicator time base.
In the context of our system, we can use the XLDA or FIFO_WTM_IA flag. The XLDA or FIFO_WTM_IA flag will go high when there is either data ready to be consumed, or when a watermark has been hit once data has filled the FIFO enough. Assuming that the time for the processor to consume the accelerometer buffer over SPI is deterministic and consistent, we only need to ensure, then, that the time propagation between data coming in and a flag being risen high is deterministic and fixed. We also want to ensure that the time between the flag being risen and the routed output INT signal going high is also deterministic and fixed. Is there a timing diagram that shows exactly on which clock pulses do flags get pulsed, and which clock pulses the routed INT output get pulsed?
