Questions regarding the I-TCM and D-TCM on STM32N6

[Einstein_rookie_version]

Hello, I'm currently writing a bachelor thesis regarding the model deployment inside the NPU. I'm writing about the theorical part of the thesis. And I was reading the RM0486 Reference manual. But I found one thing unexpected, from the page 1023, this figure

have a I-TCM and D-TCM above the CPU and seems to have a connection with the NPU and CPU.

However, I never have any experience with these storage devices... I have the project to make right inference inside the NPU which is modified from the get started project of the DK Board, the CubeIDE project only activated the D and I cache explicitly in the code. (of course AXIRAM 3456 and XSPI...) but no codes regarding the I TCM and D TCM. from other documentations, I also have rare infos about them. 

So my question is: Are these I-TCM and D-TCM used inside the get started project of the DK Board ? or are they used in the runtime without any explicit code? Are there more documentation about what does they do for the NPU reference? For normal ai inference (without NPU, only CPU), are I TCM and D TCM also used implicitly in runtime or not?

Thanks a lot in advance!

[TDK · Accepted solution]

They are never implicitly used. You need to specify code and data to live there and make the appropriate linker and code changes to move it to that space at startup.

These are features of the Cortex core, rather than something STM32 decided, which is why there is limited information in ST's documentation. Unfortunately, the ARM documentation is quite lacking in this regard.

Arm Cortex-M55 Processor Technical Reference Manual r0p2

The main takeaway is they have better performance than other RAM on the chip.