Not seeing boot context in FSBL

[cbcooper]

I've got an STM32MP135AAE3 for which I'm writing my own FSBL.  It's basically working!

There are two scenarios:

1) Chip set to serial boot; the BootROM wakes up and I use STM32_Programmer_CLI.exe to send it my FSBL which it stores in SYSRAM, BootROM then passes execution to my FSBL

2) Chip set to boot from eMMC; BootROM wakes up, sees my FSBL in eMMC, copies it from eMMC to SYSRAM, passes execution to it

It would be helpful for my FSBL to know which scenario it is, and according to STM32 MPU ROM code overview I should be able to inspect the first 512 bytes SRAM2 for a bunch of boot information as defined in this H file.  It also says SRAM2 is for "ROM code secure data" and SRAM1 is for "ROM code non-secure data" and I'm running in non-secure mode so maybe it's actually SRAM1 for me?

In any case, I've got my LD file set up so nobody touches the first 512 bytes of either SRAM1 or SRAM2:

MEMORY {
    SYSRAM (rwx)   : ORIGIN = 0x2FFE0000, LENGTH = 128K

    SRAM1 (rwx)    : ORIGIN = 0x30000000, LENGTH = 16K
    SRAM2 (rwx)    : ORIGIN = 0x30004000, LENGTH = 8K
    SRAM3 (rwx)    : ORIGIN = 0x30006000, LENGTH = 8K
    
    SRAM_A (rwx)   : ORIGIN = 0x30000200, LENGTH = 15872
    SRAM_B (rwx)   : ORIGIN = 0x30004200, LENGTH = 15872
}

and then nothing goes in SRAM1, SRAM2, or SRAM3; everything goes in SYSRAM, SRAM_A, or SRAM_B.  When my main() gets called I have it dump the first 128 bytes of SRAM1 and SRAM2 and here's what i see:

SRAM1+0x0000: C7 7F B5 74 E8 31 92 63 02 C1 5F 30 B0 67 C8 A0 49 66 A4 07 AA 12 40 27 CF 72 58 25 4C 56 40 70 
SRAM1+0x0020: 00 00 00 00 00 00 00 00 68 48 A3 43 73 3A 73 91 2A 0D 8E C4 B1 AE 41 E1 70 9B B1 19 BA FB D1 49 
SRAM1+0x0040: 01 00 00 00 00 00 00 00 63 D0 B5 47 C7 43 17 89 E4 C9 D0 A8 8F E6 10 8B DA C3 E7 C8 00 00 00 00 
SRAM1+0x0060: 00 00 00 00 00 00 00 00 03 00 00 00 FF 00 00 00 FF 00 00 00 48 06 00 00 FE 00 00 00 00 00 00 00 

SRAM2+0x0000: F7 6B 4F 1E 97 3C 18 AD 0A A5 9D 49 DC 56 ED D8 45 AC E8 05 7D 92 53 2B 7D F6 C1 84 38 71 20 05 
SRAM2+0x0020: F6 C5 2D 58 29 88 E0 7E F3 62 94 E9 62 05 B6 5F FD FA AC 64 72 BC DC C0 8B 80 A5 3C 13 A8 4E 71 
SRAM2+0x0040: 2C 9E 1D 9F 80 0D 84 07 A1 C4 1A 07 16 C9 BC DE 7B B3 5E 06 64 7D 91 03 28 13 E5 E3 6A DE CB 30 
SRAM2+0x0060: 77 2B CA D9 A0 C5 9B 73 43 84 E2 DD 93 DC 86 DD AF 61 10 20 19 4D F9 0C 02 00 02 00 B0 03 95 6C

Neither of those match any of the magic numbers I see in boot_api.h nor any byte pattern in my LIST file.

The bytes aren't random - when I change the code, upload a new FSBL, power cycle the chip, and run again, the values are identical except for a few bits here and there:

SRAM2+0x0060: 77 2B CA D1 A0 C5 93 73 43 84 E2 DD 13 DC 06 DD AF 61 10 28 09 4D F9 8C 02 00 02 00 B0 03 D4 64 
SRAM2+0x0060: 77 2B CA D9 A0 C5 9B 73 43 84 E2 DD 93 DC 86 DD AF 61 10 20 19 4D F9 0C 02 00 02 00 B0 03 95 6C 

What am I seeing, and why am I not seeing the boot info?