STM32mp25D hanging at intializing BL32, no errors.

[AN_turner]

I am struggling with getting a STM32mp25D board flashed, it hangs at BL32 (see output below). It does have one warning "WARNING: Could not enable VRSEL for vddio2", but I don't think that is relevant to the hanging at BL32 (but I could be wrong). I have successfully flashed a STM32mp25F-EV1 board, that works fine. Seeing as the difference between the D and F flavor is that F supports secure boot, I have attempted to tweak OPTEE settings, such as building  OP-TEE OS with configuration CFG_STM32MP_PROFILE=system_services, as suggested here. I have also attempted to set BOOTSCHEME_LABELS = "opteemin" in the boot scheme section of the stm32mp25.conf file. Someone else on the team is also tweaking firewall/security settings, also with no success. I'm not sure exactly what they have attempted on that front, however. 

I am wondering if someone else has run into this problem/has a solution? I'm also unsure if I'm barking up the wrong tree thinking that the issue lies with OPTEE/firewall settings, and its actually something else entirely?

OUTPUT FROM UART8

NOTICE: CPU: STM32MP257DAI Rev.Y
NOTICE: Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06
NOTICE: Reset reason: Power-on reset (por_rstn) (0x2035)
INFO: PMIC2 version = 0x11
INFO: PMIC2 product ID = 0x21
INFO: FCONF: Reading TB_FW firmware configuration file from: 0xe011000
INFO: FCONF: Reading firmware configuration information for: stm32mp_fuse
INFO: FCONF: Reading firmware configuration information for: stm32mp_io
WARNING: Could not enable VRSEL for vddio2
INFO: Using USB
INFO: Instance 2
INFO: Boot used partition fsbl1
NOTICE: BL2: v2.10-stm32mp2-r1.0(debug):lts-v2.10.5-dirty(7c229848)
NOTICE: BL2: Built : 16:19:31, Jun 28 2024
INFO: EventBuffer0: BuffArea=e03f000 DmaAddr=0e03f000 CoherentMapAddr=0xe03f000
INFO: dwc3_set_dev_speed = HighSpeed
INFO: DFU USB START...
INFO: Event: Link Status Change : ON(0)
INFO: Event: Link Status Change : Early Suspend(5)
INFO: Event: Link Status Change : L2(3)
INFO: Event: Suspend
INFO: USB Suspend mode
INFO: Event: Device Reset
INFO: Event: Device Connection Done
INFO: dwc3_get_dev_speed = HighSpeed
INFO: Event: Link Status Change : ON(0)
INFO: Event: Link Status Change : Early Suspend(5)
INFO: Event: Device Reset
INFO: Event: Device Connection Done
INFO: dwc3_get_dev_speed = HighSpeed
INFO: Event: Link Status Change : ON(0)
INFO: phase ID :2, Manifestation 0 at e0086b0
INFO: Send detach request
INFO: Receive DFU Detach
INFO: DFU USB STOP...
INFO: BL2: Loading image id 26
INFO: Loading image id=26 at address 0xe041000
INFO: Image id=26 loaded: 0xe041000 - 0xe049650
INFO: BL2: Doing platform setup
INFO: RAM: LPDDR4 32bits 640000kHz
INFO: Memory size = 0x80000000 (2048 MB)
INFO: DFU USB START...
INFO: Event: Link Status Change : ON(0)
INFO: Event: Link Status Change : Early Suspend(5)
INFO: Event: Link Status Change : L2(3)
INFO: Event: Suspend
INFO: USB Suspend mode
INFO: Event: Device Reset
INFO: Event: Device Connection Done
INFO: dwc3_get_dev_speed = HighSpeed
INFO: Event: Link Status Change : ON(0)
INFO: Event: Link Status Change : Early Suspend(5)
INFO: Event: Device Reset
INFO: Event: Device Connection Done
INFO: dwc3_get_dev_speed = HighSpeed
INFO: Event: Link Status Change : ON(0)
INFO: phase ID :3, Manifestation 1 at 872f2b7a
INFO: Send detach request
INFO: Receive DFU Detach
INFO: DFU USB STOP...
INFO: BL2: Loading image id 1
INFO: Loading image id=1 at address 0xe000000
INFO: Image id=1 loaded: 0xe000000 - 0xe000326
INFO: FCONF: Reading FW_CONFIG firmware configuration file from: 0xe000000
INFO: FCONF: Reading firmware configuration information for: risaf_config
INFO: RISAF2: No configuration in DT, use default
INFO: FCONF: Reading firmware configuration information for: dyn_cfg
INFO: BL31 max size = 0x17000 (94208B)
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xe000000
INFO: Image id=3 loaded: 0xe000000 - 0xe0114c0
INFO: BL2: Loading image id 19
INFO: Loading image id=19 at address 0x81fc0000
INFO: Image id=19 loaded: 0x81fc0000 - 0x81fc3758
INFO: BL2: Loading image id 4
INFO: Loading image id=4 at address 0x82000000
INFO: Image id=4 loaded: 0x82000000 - 0x8200001c
INFO: OPTEE ep=0x82000000
INFO: OPTEE header info:
INFO: magic=0x4554504f
INFO: version=0x2
INFO: arch=0x1
INFO: flags=0x0
INFO: nb_images=0x1
INFO: BL2: Loading image id 8
INFO: Loading image id=8 at address 0x82000000
INFO: Image id=8 loaded: 0x82000000 - 0x820fc628
INFO: BL2: Loading image id 2
INFO: Loading image id=2 at address 0x84400000
INFO: Image id=2 loaded: 0x84400000 - 0x84414450
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x84000000
INFO: Image id=5 loaded: 0x84000000 - 0x841c49b8
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xe000000
INFO: SPSR = 0x3cd
INFO: ARM GICv2 driver initialized
NOTICE: BL31: v2.10-stm32mp2-r1.0(debug):lts-v2.10.5-dirty(7c229848)
NOTICE: BL31: Built : 16:19:31, Jun 28 2024
INFO: BL31: Initializing runtime services
INFO: BL31: Initializing BL32

[Olivier GALLIEN]

Hi @AN_turner 

"WARNING: Could not enable VRSEL for vddio2" is typically related to IO configuration to 1.8V. 

Find below what "Sidekick" provide as answer and that seems consistent. 

1. OTP Programming Requirement for VRSEL

The warning "Could not enable VRSEL for vddio2 in TF-A" typically indicates that the attempt to set the voltage range selection (VRSEL) for the VDDIO2 domain failed. This is most often due to the associated HSLV OTP bit not being programmed. The VDDIO2VRSEL bit in the PWR_CR7 register only takes effect if the corresponding HSLV OTP bit has been set. If this OTP bit is not programmed, enabling VRSEL will not work, and the warning is triggered.

2. Proper Sequence for Enabling VDDIO2 1.8V Mode and VRSEL

To correctly enable VDDIO2 1.8V mode and VRSEL, the following sequence must be followed:

1. Enable VDDIO2VM by setting VDDIO2VMEN in PWR_CR7.
2. Wait for the VDDIO2VM wake-up time.
3. Wait until VDDIO2RDY is set in PWR_CR7.
4. If VDDIO2 is in the 1.8V range, set VDDIO2VRSEL in PWR_CR7.
5. Optionally, retain the configuration by setting VDDIO2VRSTBY in PWR_CR7.
6. Set VDDIO2SV in PWR_CR7 to remove power isolation.

Failure to follow this sequence, or missing any step (especially OTP programming), can result in VRSEL not being enabled.

3. Other Conditions Preventing VRSEL Enablement

• Incorrect Supply Voltage: Setting VDDIO2VRSEL to 1 (1.8V) when VDDIO2 is actually at 3.3V can damage the device and is not allowed.
• Power Isolation: If VDDIO2 supply is not present or not validated (VDDIO2SV not set), the I/Os are isolated, and VRSEL setting is ineffective.
• Boot Chain Responsibility: The boot chain (e.g., TF-A) must configure the IOs mode according to the product configuration. If not done, VRSEL may remain unset.
• Reset Behavior: The VDDIO2VRSEL bit is reset by application reset or system reset, depending on the VDDIO2VRSTBY setting.

---

Summary

The warning "Could not enable VRSEL for vddio2" in TF-A is most commonly caused by the required HSLV OTP bit not being programmed, which is necessary for the VDDIO2VRSEL bit to take effect. Ensure the OTP is programmed, follow the correct sequence for enabling VDDIO2 1.8V mode, and verify all supply and configuration conditions are met.

For additional support or to discuss your specific application with ST experts, you’re welcome to join conversations in STM32 forums.

Hope it help

Olivier