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Why NRST pin as GPIO mode is holding the MCU under reset

STea
ST Employee

Introduction

The NRST pin can be configured in GPIO mode and this is handy for small packages such as STM32C011 8-pin package. In this article, we explain the constraints and potential workaround of using NRST pin in GPIO mode.

STM32C011D6Yx 8pin package from CubeMXSTM32C011D6Yx 8pin package from CubeMX

1. NRST pin characteristics

The NRST pin is a bidirectional pin with an open-drain MOS transistor and an internal pull-up resistor. It is designed to reset the STM32 internally from various sources as well as externally. The key characteristics of the NRST pin are summarized in Table 52 of the DS13866:

STea_0-1733847673174.png

2. NRST pin in GPIO mode

When configuring the NRST pin in GPIO mode, it is essential to ensure that the level on the NRST pin can exceed the minimum VIH(NRST). If this condition is not met, the device will not exit the power-on reset (POR). This requirement applies to any NRST configuration set through the NRST_MODE[1:0] bitfield, including the GPIO mode.

3. Why a minimum voltage is necessary

Upon power-on, the NRST pin must exceed the minimum VIH(NRST) level to exit the reset state. If the NRST pin is held low during power-on, the device remains in the reset state because the option bytes (OB) have not been loaded yet. This behavior ensures that the device can be recovered even if the NRST pin is configured as GPIO. By putting the reset pin low during POR, access to the debug pins is still possible.

4. Workaround by using a serial resistor

To address the issue of ensuring the minimum voltage on the NRST pin, a workaround involves using a serial resistor between the NRST pin and the external signal. This setup creates a resistor bridge between the NRST internal weak pull-up and the serial resistor. The user must calculate the appropriate value for the serial resistor to ensure that the signal exceeds the VIH(NRST) level when the external signal is low. This configuration allows the NRST pin to be reconfigured as a GPIO while ensuring that the embedded pull-up is removed.

5. Implementation steps

5.1. Calculate the serial resistor value

Determine the appropriate value for the serial resistor to ensure that the signal on the NRST pin exceeds the VIH(NRST) level when the external signal is low. 
STea_2-1733828435310.png

 


R_serial = (VIH*RPU)/(VDD-VIH)
For example: If VDD = 3.3, RPU = 40 kΩ, VIH = 0.7VDD => R_serial = 90 kΩ. 

5.2. Connect the serial resistor

Place the serial resistor between the NRST pin and the external signal.

5.3. Ensure proper placement

Ensure that the external capacitor on the NRST pin is placed as close as possible to the device to minimize parasitic resets.

Conclusion

In STM32C0 products, the NRST pin can be used in GPIO mode unless a minimum voltage is ensured on the reset pin to exit reset. By using a serial resistor between the NRST pin and the external signal, it is possible to achieve the required voltage level and configure the NRST pin as GPIO. This workaround ensures the proper functioning of the microcontroller and allows for the use of all available GPIO pins, including the NRST pin.

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Last update:
‎2024-12-19 04:30 AM
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