on
2024-04-23
07:45 AM
- edited on
2024-05-23
05:32 AM
by
Laurids_PETERSE
Some external USB HS PHYs compatible through the ULPI interface are detailed in Table 12, compatible USB HS PHY in AN4879. However, not all transceivers could be listed in the application note. Compatibility checking is necessary before choosing your ULPI transceiver. This article intends to facilitate the check of compatibility of ULPI PHY and STM32.
The clock timing requirements written in the ULPI specification are important to ensure that the device can wake up and respond to the host's chirp signal in a timely manner. Additionally, that the clock frequency is stable enough for reliable communication.
Ensure that ts(IN) = 5 ns ≤ (Clock period (tCLK) – tv(OUT)max) is used for proper operation
According to datasheet "USB3300 Table 6-2: UPLI interface timing output clock:"
According to datasheet "STM32F77 table 96. Dynamic characteristics: USB ULPI" as an example:
Control in (ULPI_DIR, ULPI_NXT)
tDC/tDD Data/control output delay (assuming @3V3) 8 ns
Clock period (tCLK) – tv(OUT)max = 1/60(MHz) – 8 ns = 8.6 ns
ts(IN), which is tSC, tSD set-up time (control in, 8-bit data in) equal to 5 ns.
Around 8.6 ns setup time for this PHY is sufficient.
Caution: @1V8 5.6 ns is risky, so you should look for a different ULPI PHY to meet the requirements.
The ULPI specification provides specific requirements for the timing of all control and data signals that are used in the ULPI interface. This includes requirements for signal setup time, hold time, and output delay, to guarantee accurate reception by the receiving chip.
Datasheet DS00001783C USB3300 (microchip.com)
Application note 4879: Introduction to USB hardware and PCB guidelines using STM32 MCUs