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Summary
This article represents Part II of a two-part series addressing methods in which to minimize the effects of external component noise and interference on the STM32WB and STM32WL series of devices. Part I focused upon the description of the various noise processes and their impact. Part II will focus on examining how to reduce and mitigate the degradation effects.
1. Overview
It is very common for switched mode power supply circuits and systems to be present on a PCB, simply due to efficiency provided by such as solution. SMPS converters such as the buck boost and boost converters provide a wide range of advantages. When integrated with RF circuitry, care must be taken to ensure that the spurious effects generated by the SMPS does not affect the RF or analog circuitry.
In addition, this document also addresses decoupling capacitor placement and strategy. It is common to insert a low frequency, mid frequency, high frequency capacitor scheme for decoupling. While this is correct in principle, there are drawbacks if not implemented properly.
2. Power Supply Noise
Figure 1 shows the system models which will be demonstrated. The base circuitry for demonstration purposes is the STM32WB Nucleo board. Figure 1(A) demonstrates a SMPS power supply driving the STM32WB device resident on a Nucleo board directly. Figure 1(B) inserts a low drop out (LDO) in between the SMPS and STM32WB device.
Figure 1: Power Supply Feed Models
2.1 LDO Functionality
The presence of the LDO, placed between the SMPS and target wireless device is always the desired solution. A good quality LDO will provide excellent common mode rejection ratio (CMRR) contributing toward removing low frequency degradation effects normally introduced by the SMPS. This can be viewed as a sort of filtering device. While it does add to bill of material (BOM), the positive impact provided by this solution may outweigh the trouble shooting and optimization time. It is recognized that this solution may not always be possible. How to work with an existing SMPS driving a RF device is addressed further in this document.
2.2 Baseline Performance
For all comparisons, a baseline is established. This reference baseline is established using the STM32WB Nucleo board with internal SMPS enabled. Figure 2(a) presents the time waveform and Figure 2 (b) represents the baseline spectrum waveform with CW mode enabled. Under these conditions, a packet error rate (PER) of less than 5% is achievable with a -92 dBm input signal level.
This measurement is taken directly at the SMPS feedback inductor input. It is observed that there is very little noise or ripple and only small spikes when the transmitter is enabled. The spectrum is also very clean with no visible noise or spurious signals.
Figure 2: STM32WB Nucleo Board SMPS Time and Frequency Baseline at RF CW
To characterize the effects of power supply noise and power supply spurious, various external SMPS configurations were used as a voltage (Vdd) source input for the STM32WB. In addition, SMPS emulation was developed and generated through a STM32L476 Nucleo board. With this board, various custom noise patterns were generated providing characteristic of varying peak, ripple, noise and frequency range.
2.3 External SMPS Performance
Figure 3 displays the time and frequency output as obtained from a lightly loaded 5 V to 3V3 buck boost converter. The SMPS output consists of a high frequency component and low frequency component. The effect of the low frequency component is visible in the spectrum plot. The spectral properties are also shown. Note the Spectrum distortion in the areas of the carrier.
In Figure 4, the ST32WBL476 was utilized to emulate the profile of the external SMPS. This approach provides the ability to modify frequency, ripple amplitude and time dependent profiles. Note that the repetitive ramp with fast rise time, significantly affects the noise floor of the CW carrier.
Figure 3: Time Domain Output of External SMPS and Impact on RF at CW
Figure 4: High Frequency Ramp and Sweep Generated Via STM32L4xx
In Figure 5, the STM32L476 programming was modified to provide a series of pulses, with varying frequency sweep and time characteristics. It was possible to capture the effect of this time waveform on the spectrum analyzer display. Note that when there is no degradation, the carrier output is clean (left side of the spectrum plot) however, when the time pulses are present, the spectrum is distorted and effects the location signal to noise ratio at that time. As the STM32WB and STM32WL devices are time division based, the interference presents a rolling effect. This effect will degrade or block some bursts but not others. This effect is observed through a time varying packet error rate when no other link conditions are varying.
Figure 5: Variable Frequency Pulsed Generated Via STM32L4xx
2.4 Mitigation
In circumstances where a LDO cannot be inserted in between a SMPS converter and the wireless device, the following circuit, as shown in Figure 6 is recommended and has proven to work.
Figure 6: Filter Structure for External SMPS Integration
On the left, the high level representation of a typical converter is shown with its local feedback. To reduce the negative amplitude and frequency effects of the converter, it is necessary to provide an external filter with narrow cut off to reduce the amplitude and frequency components of the SMPS. This filter will work to reduce the peak and average ripple observed at the output. In addition, as there may be more than one SMPS present on a typical board, it is recommended to include a second filter, based upon a ferrite bead topology. This may be required to attenuate high frequency components resulting from the many converters and high speed digital circuitry.
As a general rule, the peak-to-peak ripple entering the STM32WB power pins should be maintained to a level of less than 20 mV p-p when the update frequency of the external SMPS resides within the 0 – 100kHz region.
- PCB Layout and Decoupling Guidance
In addition to power supply and digital noise degradation, PCB ground plane organization and decoupling strategy also require careful attention.
In a typical board layout may be represented as shown in Figure 7.
Figure 7: Example Decoupler and IC Placement
The PCB consists of a power supply device and IC’s with bulk decoupling around each of the integrated circuit devices. The typical approach is to provide decoupling capacitors, close to the IC power pins, with each capacitor spanning different frequency bands. While having more capacitors is not a negative approach, location of the capacitors and mounting relative to ground planes and power planes is very important.
When a decoupling capacitor is employed, it is acting as a local energy storage. The decoupling capacitors, in a similar method to a battery requires time to charge and discharge. The concept of using a capacitor as a decoupler essentially means that the system or PCB is trying to avoid rapid changes in voltage. When input voltage dips, the capacitors try to mitigate this effect by providing the required energy to maintain balance and if spikes are present on the supply lines, the capacitor tries to absorb this energy.
In context of this discussion, the charging and discharging function may span an area of a plane or several planes. In so doing, the placement of the capacitor is important. As previously discussed, the ground planes, power planes and signal planes form a reactive model. The decoupling capacitors and vias, form a mesh like electromagnetic circuit providing many paths for signal and noise to travel. Therefore, care should be taken in the placement of the decoupling capacitors and devices in general.
The negative aspect of not properly considering a decoupling strategy is many and also depends upon the operational frequency or frequencies of the board. One negative aspect is that of not achieving the expected suppression from the decoupling capacitors and ground plane. From the point of view of electromagnetic circuit analysis, the structure represents a network that may have resonance(s) at unwanted frequencies. This creates an EMC problem with both steady and transient negative impact
Reviewing documentation models generated through SPICE, manufacturer data sheets, the capacitor high frequency model maybe represented as shown in Figure 8. The capacitor consists of the base capacitance, internal inductance (ESL) and a resistive (ESR) component. All these elements are frequency dependent and can combine to contribute negative side effects.
The concept of placing many capacitors in parallel is based upon the concept that the internal equivalent series inductance (ESL) of these capacitors, as presented in Figure 8, is effectively reduced by the factor, 1/N. Similar to parallel resistor theory. However, as shown in Figure 8, this parallel reduction is not always the case at higher frequencies as the equivalent circuit becomes much more complex.
Figure 8: One Model of a High Frequency Capacitor
The placement of these capacitors relative to the IC, the placement of these capacitors relative to other capacitors and the interconnection of these capacitors within the plane structure cannot be ignored.
Figure 9 expands the capacitor model and includes some examples impairments that are introduced when attention is not given to layout parameters. Even a small PCB trace, when trying to connect to ground, will add inductance that when considered with the overall capacitor model, introduces a reactive circuit with definite resonances.
Figure 9: Decoupler Input / Output Configurations
In summary, the goal is to minimize trace length as this produces an inherent inductance. The inductance not only serves to provide a resonant circuit parameter but also, can act as a RF block to high frequencies preventing the intended purpose of the decoupling capacitor. Some examples are shown in Figure 9 but there are many more. The approach is normally determined by the IC power and ground configuration and the printed circuit board plane structure. In the next section, a discussion of the PCB planes, capacitor placement and Vias is expanded further.
3.1 PCB Plane Parameters
The effect of dielectric constant, Er, and connection of decoupling capacitors within PCB planes is discussed. Consider the 4-layer board shown in Figure 10. The PCB consists of a metal plane for digital, RF and analog signal paths, RF/analog ground plane, a secondary metal plane for digital ground paths and finally a general purpose signal plane. Each ground plane is separated by a dielectric layer, Er.
The connection combinations shown in Figure 10 provide one common property, and that is to reduce coupling inductance between devices and to minimize plane inductance. The vias to the various ground planes are shown and their structure is intentional. The presence of the dielectric may invite currents to flow on internal layers affecting the return path. These paths may form circuit impedances that may work in favor or against the final goal.
The goal is to reduce plane and path inductance in order that the effect of the capacitor dominants as much as possible. With reference to Figure 10, previously presented, the desired placement of capacitors on a PCB structure is shown. Note the orientation and connections for each scenario.
Figure 10: Examples of Desired Connection Approach With 2 or More Layers
The placement strategy and plane strategy are described further using basic field theory and also by further expanding the capacitor model. One of the connection options as shown in Figure 10 is expanded to demonstrate current flow. If it assumed that current flows from the positive terminal (metal plane) to the negative terminal (ground plane) then drawing the current flow provides the diagram as shown in Figure 11.
Figure 11: Field and Current Flow Description
The Via can be modelled as a narrow wire carrying current. In effect, the current induces a field component in the direction shown. With proper placement, some of the unintended side effects can be minimized. In addition, due to the plane structure, there is also current flowing in the ground plane. Figure 12, summarizes the new capacitor model including Via lumped element impedance and ground plane routing.
Figure 12: Expanded Capacitor, Via, Ground Plane Model
There are two observations that can be concluded from the diagram of Figure 11 and Figure 12. The first, is to provide the ground return ground path(plane) as close as possible to the generating plane. This in order to minimize any plane effects. This will constrain field flow to a tight localized area. Second, when placing multiple capacitors, it is important to place the capacitors to minimize any stray capacitance and unintended inductance.
To fully observe this effect and to be able to control and evaluate this type of resonance, requires an electromagnetic package such as CST or ADS. As a conclusion, the above figure when simulated, will show that it is not the value of capacitance that is important but rather, the placement of the capacitor relative to the IC and relative to other capacitors.
3.2 IC Decoupling
If the only elements present on a PCB were discrete passive components, the layout and placement of the passive devices could be optimized. However, when an IC is included in the design, maintaining the design rules presented becomes a challenge. The challenge is encountered due to the routing requirements of the input/output (IO) pins of the IC.
Figure 13 shows a possible scenario. In order to optimize the routing and minimize trace lengths of critical signals, these signals usually take precedence, and the decoupling may take a lesser precedence during layout. Regardless of the situation, trying to maintain an optimized decoupling strategy becomes a challenge.
The figure presents some options. As many mixed signal wireless IC’s possess a ground pad or ground slug, there are some strategies that will work well. In Figure 12 (A), it is not possible to maintain the routing strategy previously presented. In this case, it is required to maintain the line lengths as short as possible and connect to the required ground and power planes as soon as possible.
In Figure 13 (B) a strategy is shown to assist in locations where several decoupling capacitors may be required to be inserted in parallel. Finally, in Figure 13 (C), another strategy is shown. With board manufacturing rules allowing, a mix of capacitors located around and below the IC, providing direct path between PCB planes is also an option to consider.
Figure 13: Example Placement With IC
The PCB layout strategy when many components are in place should reflect the optimization of decoupling and layout with a localized area. One example is to ensure the decoupling around a mixed signal device is optimized. Following the strategy presented, will provide a means of reducing ineffective decoupling that may lead to unwanted emissions and fields. This strategy can be applied on a localized (IC by IC) basis.
In between devices, the structure of the ground planes and signal planes should be analyzed from an electromagnetic field aspect. The Vias, ground plane decoupling, IC ground and Vdd connections all form a complex reactive structure. With proper simulation tools, these items can be analyzed and adjusted prior to manufacturing the PCB itself, resulting in reduced time in the lab debugging the complex effects introduced by the subjects discussed in this article.
Conclusion
This article has presented several areas where careful attention to system and board level design will mitigate long sessions of debug in the lab. While not all of the recommendations can be implemented fully on every board design, implementing some of the recommendations will assist in complex, difficult to trouble shoot side effects.