Posted on July 12, 2013 at 17:42Here is the problem situation: I use a 16KB internal flash sector to store configuration parameters. Code in the flash performs the flash erase and write operation, which works fine. Next I enable the WWDG windowed watchdog and find out the maximum possible timeout period for WWDG in an F4 is:
lower PCLK1 to /16, 10.5MHz
WWDG divider is PCLK1/4096, 2564 Hz
WWDG prescaler /8, 320 Hz per WWDG timer tick
So for the maximum WWDG period I set the minimum to 1 count (126), max window to 127 count, yielding a WWDG timeout of /63, about 5Hz or 200msec.
However, the F405 datasheet says the worst case 16KB ease time is 800msec, so the WWDG will always timeout in the middle of an erase. Okay, I move the erase to SRAM so I can reload the WWDG during a flash erase without stalling insturctions. This also works fine at RDP level 0.
But now I'm executing code in SRAM with the read protection level set to 1, no flash access from SRAM including erase (according to PM0081 flash programming manual). It appears there is no way to use both the WWDG watchdog and in application programming wiht RDP level 1.
Now the IWDG can be set to several seconds for a timeout, so there is one watchdog still working, but it appears the WWDG is incompatible with RDP level 1. Has anyone come across this problem?
Jack Peacock
#wwdg-flash-rdp
