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STM32H755 OpenAMP arbitrary two way messaging

Jonathan173
Visitor

Hi,

I have been using OpenAMP on an STM32H755ZIT MCU recently but ran into an issue where the mcu would go into hard fault caused by a bus fault somewhere in virtio code. The issue occurs only after a while, after dozens of messages have successfully been passed in both directions.

I haven't been able to exactly pinpoint the violation because i get an IMPRECISERR bus error and have not been able to disable write buffering (I tried with an MPU config which failed and the config register value from https://community.st.com/t5/stm32-mcus/how-to-debug-a-hardfault-on-an-arm-cortex-m-stm32/ta-p/672235, but that doesn't seem to exist on this mcu). I did seem to get the rough area of the fault with the stack trace which pointed me to `uint16_t vq_ring_add_buffer`. Because of the disassembly view and register state before the fault I think the error relates to a str in the 0x20010000-0x2001ffff memory region which is the DTCM memory region of the CM7 core according to the datasheet. This doesn't make much sense to me so there is probably something else wrong still.

After rereading the inter processor communication AN (https://www.st.com/resource/en/application_note/an5617-stm32h745755-and-stm32h747757-lines-interprocessor-communications-stmicroelectronics.pdf) I started second guessing whether my use of OpenAMP is intended, because I initiate messages from the master and slave arbitrarily instead of a request-response flow. I use OpenAMP to send commands to the slave which runs a real-time FOC loop for motor control and it sends back status updates to the master about the execution of the commands.

So my questions are 1. is my use intended with OpenAMP? 2. if not could I open multiple channels where either core is master of one and slave of the other? 3. if the issue is somewhere else, how can I further debug this? How can I get a precise bus fault with the exact offending address on this MCU?

Thanks in advance.

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