STM32f429II revisions and Errata fix confirmation

[Krishna M]

Posted on August 17, 2017 at 12:22

Hello,

As per the STM32F42xx errata sheet (

/external-link.jspa?url=http%3A%2F%2Fwww.st.com%2Fcontent%2Fccc%2Fresource%2Ftechnical%2Fdocument%2Ferrata_sheet%2F38%2Fe6%2F37%2F64%2F08%2F38%2F45%2F67%2FDM00068628.pdf%2Ffiles%2FDM00068628.pdf%2Fjcr%3Acontent%2Ftranslations%2Fen.DM00068628.pdf

) the errata no , '2.11.5 Interruption of CPU read burst access to an end of SDRAM row',this issue is Fixed in the Device Revision 3,4 and B.

As per table 4 mentioned in the errata  , the work around of 2.11.5 need not to be applied on device revision 3,4 and B.

But as per our experiments, we are observing this issue

https://community.st.com/0D50X00009XkYFOSA3

even on Device Revision 3,4 and B.

At the same time, if we repeated the experiment after applying the work around say Enable the read FIFO by setting the RBURST bit in the FMC_SDCR1 register, the issue

https://community.st.com/0D50X00009XkYFOSA3

not observed

Please let us know whether the work around Enable the read FIFO by setting the RBURST bit in the FMC_SDCR1 register is applicable for all device revision such as revision â€œAâ€�, “Yâ€�, “1â€�, “3â€�, “4â€�, “Bâ€�?

Thanks and Regards,

Krishna Prasad M

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[Tesla DeLorean]

Posted on August 17, 2017 at 14:18

This sounds like something you need to be reviewing with the FAE assigned to your account.