Posted on May 22, 2013 at 12:20I am using an STM32F4 to monitor port conditions and stream this data to an SD card. My current architecture uses DMA2 stream 1 in double buffer mode to sample the GPIOE IDR registers at 5 MHz. Once a buffer is full I stream this to the SD card using the CPU to manually fill the SDIO Tx Fifo. This works well and I can acheive ~10 MB/s throughput to the SD card. To acheive this speed with the SD card I send the multiblock command and kickoff the data path state machine. I have determined that the DPSM and sd card will wait for data just fine BETWEEN 512-byte block transfers. If delay occurs during a block transfer then the SDIO tx fifo can underrun. To complete the SD write I either wait for my max data length to occur or other stop conditions upon which I send the stop cmd to the SD card.
I am currently trying to transition the block transfer to the SD card to use DMA stream 3 but I believe I need the DMA to be the flow controller since the data length can be less than the max data length set in the SDIO. My progress so far has acheived inconsitent results. Sometimes my DMA to sd card transfer works, other times I get a SDIO Tx underrun. I have tried several different DMA configurations with some giving tx underrun or DMA fifo errors. I have the DMA stream 3 priority set to very high and stream 1 set to high. Has anyone successfully setup the DMA to be the flow controller when transfering data to SDIO?
