SDADC Limitations Explained

[kevin2399]

Posted on August 08, 2014 at 15:07

After reading through the promotional material, datasheet and reference manual for the STM32F3's SDADC and spending a few days trying to obtain a 16KHz sampling rate, I believe some clarification of the limitations of this peripheral are in order.  For the record, these limitations should be explicitly stated in the overview of this peripheral. Until that happens, I hope this can be an informative source of information that will save others from the frustration I experienced in trying to store a single channel at 16ksps to a DMA buffer (which BTW it turns out is impossible with this device).

My reading of ST's literature led me to believe I could easily acquire samples to DMA at 16 ksps for a single channel. Here's the real story: 1) Timer-controlled conversions are limited to ~12.4 ksps, regardless of the number of channels. You CANNOT sample a single channel faster than this using a sample rate of choice. 2) A sample rate of ~16.67 ksps per second can be obtained for a single channel in CONTINUOUS MODE ONLY, when operating with the maximum SDADC_CLK of 6 MHz in normal mode. If this is the rate you want, rejoice... you hit the jackpot. 3) A sample rate of 50 ksps per second can be obtained  for a single channel in CONTINUOUS MODE ONLY, when operating with the maximum SDADC_CLK of 6 MHz in fast mode. If this is the rate you want, rejoice... you won the lottery. 4) Sampling rates between 12.4 ksps and 50 ksps can only be controlled by SDADC_CLK, which can only be set to specific divisions of the system clock, leaving very limited sample rate options. Sample rate can only be set by changing your system clock rate and/or the SDADC clock divider. In continuous mode, sampling occurs every 360 SDADC_CLK cycles in normal mode, and every 120 SDADC_CLK cycles in fast mode (after the first measurement, which still takes 360 cycles). I have not delved into the DMA capabilities in continuous mode, so I can't comment on whether it is possible to have these conversions go directly to a DMA buffer. What I can definitively state is that if you want to do timed conversions (using a timer) and store to DMA, you will be limited to ~12.4 ksps for a single channel. If someone out there has been able to accomplish this, do tell.  It would be welcome news to myself and revealing to ST support. Good luck with your SDADC applications!

[stm322399]

Posted on August 08, 2014 at 15:27

Oh really, there such a limitation in SDADC ??? Have you ever tried a user forum to get some help ?

[kevin2399]

Posted on August 08, 2014 at 15:35 My post is the result of information gained by working with ST support for two days on this issue, as well as my own experience in trying a number of experiments. As I said in my initial post, if you have been able to do better, please share rather than providing a snippy retort, which helps nobody.

[stm322399]

Posted on August 08, 2014 at 16:48

Nope, I have never experienced any F3.

However I did TIM+ADC+DMA on F103. I can set the sampling rate mostly anywhere up to 100ksps (the limitation comes from my project, not the silicon). TIM triggers ADC, ADC converts a sequence of 16 channels (understand one conversion every 10µs, not 16 conversions every 10µs, each channel after the other). End of conversion triggers DMA. Every 16 DMA transfer the CPU takes an interrupt and can compute something using the 16 conversions. I have no clue why it is not possible to do so on F3, this even surprises me as it would be a regression. But regression happens sometime.

[kevin2399]

Posted on August 08, 2014 at 17:00

I think you missed a detail in my post - I am referring to the sigma-delta (SDADC) that is available on the 'F37x series of STM32s.  I have no doubt that it could be done with the SAR ADC.

This issue really cam as a surprise to me - I designed the PCB to use the SDADC due to its linearity and improved resolution, and from reading ST's materials I thought I'd be able to do up to 50 ksps while controlling the sample rate.  I originally was planning on 8KHz, but recently discovered a need for 16KHz (which was unfortunately after the board was completed).  I did all of my verification on the STM32F373C-EVAL board, but at 8KHz :( I posted this experience because it would be very easy for someone to believe this SDADC has the ability to perform up to 50ksps at a user-defined rate, which is not the case.

[Tesla DeLorean]

Posted on August 08, 2014 at 17:22

If someone out there has been able to accomplish this, do tell.  It would be welcome news to myself and revealing to ST support.

Given the abhorrent level of support from FAE's and ST here on the forum, I really can't put much faith in having others find me solutions. The description of the F37x chip seems to be more capable than you describe, but I don't have any F37x hardware, and the STM32F3-DISCO (F303) doesn't contain an SDADC. You could change that situation by sending me some development hardware. The lack of clocking options is a problem across the family, to get to some particular frequencies you're going to have to down clock the parts, or find magic crystals.

[stm322399]

Posted on August 08, 2014 at 17:38

You right, I missed that you were using SDADC.

Reading the documentation I understand better 16,6Ksps and 50ksps (continuous, single channel). I curious to known how you configured the HW for an arbitrary sampling frequency that leads you to reach a max of 12,4ksps. Can you describe ?

[kevin2399]

Posted on August 08, 2014 at 18:17

There is an ECG example for the STM32F373C-EVAL board that uses the SDADC with TIM3 triggers using PWM mode, and DMA to automatically store the conversion results.  All you have to do to get 12.4ksps is adjust the PWM Period and Pulse settings. Running at 72 MHz system clock and SDADC at 6 MHz (SYSCLK/12), the Period value is 5806 and the Pulse value is 2903.  If you try to go to 12.5kHz (5760/2880), you will start missing conversions.

I've verified that the timer generates the conversion clocks at the proper rate, but the SDADC cannot keep up.