2015-06-14 05:13 AM
uint32_t SystemCoreClock = 168000000;
uint32_t TIM4_PWM_frequency;
uint16_t TIM4_CCR1_SRC[1024];uint16_t DMA1_TIM4_Pulse_Number = 10;
/** * @brief Configure the TIM4 CH1 as PWM out. * @param None * @retval None * made by wjandsq@163.com */void TIM4_PWM_DMA_Config(void){ GPIO_InitTypeDef GPIO_InitStruct; DMA_InitTypeDef DMA_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; TIM_OCInitTypeDef TIM_OCInitStructure; uint16_t uhTimerPeriod = 0; uint16_t i; TIM4_PWM_frequency = 500000; // 500KHz uhTimerPeriod = (uint16_t) ((SystemCoreClock /2) / TIM4_PWM_frequency) - 1; TIM4_CCR1_SRC[0] = uhTimerPeriod / 2; for(i = 1; i < 1024; ++i){ TIM4_CCR1_SRC[i] = TIM4_CCR1_SRC[0]; } RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);&sharpifdef USE_PB6_PWM // TIM4_CH1_PWM: USE_PB6 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* GPIOB Configuration: TIM4 CH1 (PB6) */ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_6; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN; GPIO_InitStruct.GPIO_Speed = GPIO_Speed_100MHz; GPIO_Init(GPIOB, &GPIO_InitStruct); /* Connect TIM4 pins to AF2 */ GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_TIM4);&sharpelse // TIM4_CH1_PWM: USE_PD12 /** TIM4 GPIO Configuration PD12 ------> TIM4_CH1 PD13 ------> TIM4_CH2 PD14 ------> TIM4_CH3 PD15 ------> TIM4_CH4 */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); /* GPIOB Configuration: TIM4 CH1 (PD12) */ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_12; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN; GPIO_InitStruct.GPIO_Speed = GPIO_Speed_100MHz; GPIO_Init(GPIOD, &GPIO_InitStruct); /* Configure GPIO pin alternate function */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_TIM4);&sharpendif RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 , ENABLE); DMA_DeInit(DMA1_Stream6); DMA_InitStructure.DMA_Channel = DMA_Channel_2; DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(TIM4->CCR1); DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) TIM4_CCR1_SRC; DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; DMA_InitStructure.DMA_BufferSize = DMA1_TIM4_Pulse; DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; DMA_InitStructure.DMA_Priority = DMA_Priority_High; DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; DMA_Init(DMA1_Stream6, &DMA_InitStructure); /* TIM4_CCR1 DMA1_Stream6 Channel 2 */ DMA_ITConfig(DMA1_Stream6, DMA_IT_TC, ENABLE); NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream6_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); /* Time base configuration */ TIM_TimeBaseStructure.TIM_Period = uhTimerPeriod; TIM_TimeBaseStructure.TIM_Prescaler = 0; TIM_TimeBaseStructure.TIM_ClockDivision = 0; TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); TIM4->CNT = 0; /* PWM1 Mode configuration: Channel1 */ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; TIM_OCInitStructure.TIM_Pulse = TIM4_CCR1_SRC[0]; TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low; TIM_OC1Init(TIM4, &TIM_OCInitStructure); TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable); TIM_ARRPreloadConfig(TIM4, ENABLE);// TIM_Cmd(TIM4, ENABLE); TIM_GenerateEvent(TIM4, TIM_EventSource_Update); /* TIM4 Update DMA Request enable */ TIM_DMACmd(TIM4, TIM_DMA_Update, ENABLE); TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);}void main(){ ..TIM4_PWM_DMA_Config();
while(1){ // for send 10 Pulse TIM4->CNT = 0; TIM4->CR1 &= ~TIM_CR1_OPM; TIM4->CR1 |= TIM_CR1_CEN; DMA1_Stream2->NDTR = DMA1_TIM4_Pulse_Number; DMA_Cmd(DMA1_Stream2, ENABLE); }}/**
* @brief This function handles DMA1_Stream4 global interrupt request. * @param None * @retval None *//** * @brief This function handles DMA1_Stream0 global interrupt request. * @param None * @retval None */void DMA1_Stream6_IRQHandler(void){ if (DMA_GetITStatus(DMA1_Stream6, DMA_IT_TCIF6) != RESET) { DMA_Cmd(DMA1_Stream6, DISABLE); DMA_ClearITPendingBit(DMA1_Stream6, DMA_IT_TCIF6); TIM4->CR1 |= TIM_CR1_OPM; // End PWM }} #tim4_ch1_pwm_dma-stm32cubemx2015-06-23 08:05 AM
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/DM00104712.pdf