Clk Configuration problem

[Mohamed GORRAB]

Posted on April 10, 2018 at 12:43

Hi, the problem is not solved, below is the clock configuration, 

Based on the figure above, 

I tried to use the different divisions /1, /8.. and the different clk (PPLCK, SYCLK, HSE...)  to obtain the correct frequency, but everytime, I have the some frequeny output that I showed on the scope, 

HSI --> 16MHZ (correct value)

SYSCLK --> 32MHZ (wrong value != 10 MHZ)

PLLCLK --> 

32MHZ (wrong value  != 10 MHZ)

.....

I added some instructions on the code to show the frequency value, and that gives 32MHZ as shown on the pictures below

Anyone have a solution please!

Thanks in advance!