2010-02-04 06:28 AM
CAN bus timings
2011-05-17 04:39 AM
2011-05-17 04:39 AM
I've now tried with my settings below on a CAN bus car and I'm getting a bus error every 10 messages. which is completly unacceptable. Can anyone offer some advice?
2011-05-17 04:39 AM
Still suffering from this problem. Can anyone offer some advice.
2011-05-17 04:39 AM
I guess you are suffering from bit timing errors. With a APB of 36 MHZ you are out of the specs for the CAN controller which needs 8 MHz clock (or a multiple of that). Try using 32 MHz APB clock (= SystemClock 64MHz) and you will be fine.
Carsten2011-05-17 04:39 AM
Hi Carsten,
Actually, you are mentioning an info which is strange/new for meCould you please clarify which ST document (section) you refer to?
armmcu.2011-05-17 04:39 AM
Excellent - you've given me some things to look into - I'll give them a go and post my results (hopefully later today).
PB2011-05-17 04:39 AM
try these combination with APB1 18 Mhz
SJW_value=CAN_SJW_1tq; BS1_value= CAN_BS1_9tq; BS2_value=CAN_BS2_2tq; Prescaler_value=3;2011-05-17 04:39 AM
Hi,
I was unable to try your suggestion (Avr.smart) as I am using an external 8Mhz clock. However. I did change the PLL multiplier to make the clock 64Mhz as suggested by Carsten so this makes my APB1 (CAN peripheral) 32Mhz. My clock function looks like this:RCC_HSEConfig(RCC_HSE_ON);
HSEStartUpStatus = RCC_WaitForHSEStartUp(); if(HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); /* PLLCLK = 8MHz * 8 = 64 MHz */ // RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_8); /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){} /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08){} }I'm thrn trying the follow CAN set-up;
CAN_InitStructure.CAN_SJW=CAN_SJW_3tq; CAN_InitStructure.CAN_BS1=CAN_BS1_10tq; CAN_InitStructure.CAN_BS2=CAN_BS2_5tq; CAN_InitStructure.CAN_Prescaler=4; CAN_Init(&CAN_InitStructure); and I see a slight improvemt - sometimes 15000 messages before an error, but then sometimes under 400 This setting CAN_InitStructure.CAN_SJW=CAN_SJW_3tq; CAN_InitStructure.CAN_BS1=CAN_BS1_12tq; CAN_InitStructure.CAN_BS2=CAN_BS2_3tq; CAN_InitStructure.CAN_Prescaler=4; CAN_Init(&CAN_InitStructure); is a little less reliable This setting: CAN_InitStructure.CAN_SJW=CAN_SJW_3tq; CAN_InitStructure.CAN_BS1=CAN_BS1_8tq; CAN_InitStructure.CAN_BS2=CAN_BS2_7tq; CAN_InitStructure.CAN_Prescaler=4; falls over after 9000 loops then 11000 loops This setting CAN_InitStructure.CAN_SJW=CAN_SJW_3tq; CAN_InitStructure.CAN_BS1=CAN_BS1_7tq; CAN_InitStructure.CAN_BS2=CAN_BS2_8tq; CAN_InitStructure.CAN_Prescaler=4; CAN_Init(&CAN_InitStructure); falls over after 3000 loops then 25000 loops Anyone?2011-05-17 04:39 AM
OK - The problem I had was I was re-initializing the CAN chip for each request. This causes data to be transmitted and if other modules are on the bus they will see this as an error and report framing errors. I simply removed the initialization and now have perfect comms with all of the settings I tried even with the board running at 72MHz (36MHz for the CAN chip).