stm32f2 FIFO_FS_SIZE

[easylwl]

Posted on April 22, 2013 at 10:14

I am use stm32f207vc usb FS devices mode.

The IN_EP = 0x82 ;  OUT_EP = 0x03; the EP1 is no use. and I want to know how to setting the FIFO_FS_SIZE?? the VCP demo is: &sharpifdef USB_OTG_FS_CORE  &sharpdefine RX_FIFO_FS_SIZE                          128  &sharpdefine TX0_FIFO_FS_SIZE                          32  &sharpdefine TX1_FIFO_FS_SIZE                         128  &sharpdefine TX2_FIFO_FS_SIZE                          32  &sharpdefine TX3_FIFO_FS_SIZE                           0   and I change to &sharpifdef USB_OTG_FS_CORE  &sharpdefine RX_FIFO_FS_SIZE                          128  &sharpdefine TX0_FIFO_FS_SIZE                          32  &sharpdefine TX1_FIFO_FS_SIZE                            0  &sharpdefine TX2_FIFO_FS_SIZE                          128  &sharpdefine TX3_FIFO_FS_SIZE                           0 the IN_EP2 can not be sent data??? #stm32f207-cdc-virtualcom-usb

[easylwl]

Posted on April 22, 2013 at 10:31

my IN_EP(0x82) and OUT_EP(0x03) max pksize =64,

[tsuneo]

Posted on April 22, 2013 at 19:42

In your former post, you've deleted the interrupt endpoint from the CDC descriptor.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex%5fmx%5fstm32%2fstm32f207%20usb%20%20only%20multiple%20of%2064%20bytes%20can%20be%20send Above assignment of endpoint buffers also suggests deletion of the interrupt endpoint. Without the interrupt endpoint, Windows CDC driver, usbser.sys, stops read out from the bulk IN endpoint (ie. IN_EP2) soon after a couple of transfer. Don't delete the interrupt endpoint from the CDC descriptors. Even if your application doesn't use the interrupt endpoint, enable it, so that it NAKs to the IN transaction from host. Tsuneo

[easylwl]

Posted on April 23, 2013 at 03:18

thank you.

but my PC usb driver is just use  2  endpoint ; I have saw the ST  note where about how to set the FIFO_FS_SIZE /******************************************************************************* *                      FIFO Size Configuration in Device mode *  *  (i) Receive data FIFO size = RAM for setup packets + *                   OUT endpoint control information + *                   data OUT packets + miscellaneous *      Space = ONE 32-bits words *     --> RAM for setup packets = 10 spaces *        (n is the nbr of CTRL EPs the device core supports) *     --> OUT EP CTRL info      = 1 space *        (one space for status information written to the FIFO along with each *        received packet) *     --> data OUT packets      = (Largest Packet Size / 4) + 1 spaces *        (MINIMUM to receive packets) *     --> OR data OUT packets  = at least 2*(Largest Packet Size / 4) + 1 spaces *        (if high-bandwidth EP is enabled or multiple isochronous EPs) *     --> miscellaneous = 1 space per OUT EP *        (one space for transfer complete status information also pushed to the *        FIFO with each endpoint's last packet) * *  (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for *       that particular IN EP. More space allocated in the IN EP Tx FIFO results *       in a better performance on the USB and can hide latencies on the AHB. * *  (iii) TXn min size = 16 words. (n  : Transmit FIFO index) *   (iv) When a TxFIFO is not used, the Configuration should be as follows: *       case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes) *       --> Txm can use the space allocated for Txn. *       case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes) *       --> Txn should be configured with the minimum space of 16 words *  (v) The FIFO is used optimally when used TxFIFOs are allocated in the top *       of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. *******************************************************************************/ also I found the ST usb  msc demo , In this demo ,it is also use  bulk mode and 2 endpoint , but it use endpoint is 0x81 and  0x01.it FIFO SIZE like this: #ifdef USB_OTG_FS_CORE  #define RX_FIFO_FS_SIZE                          128  #define TX0_FIFO_FS_SIZE                          64  #define TX1_FIFO_FS_SIZE                         128  #define TX2_FIFO_FS_SIZE                          0  #define TX3_FIFO_FS_SIZE                           0 but I use endpoint is  IN_EP2(0X82)  and OUT_EP3(0x03), how can I set the FIFO SIZE?? thanks!