2026-01-22 11:33 PM
I am working on STM32N6570-DK board. I am trying to run a code for three channels ADC+DMA, INP8, INP10, INP16. The output at USART is coming out to be zero in all three channels. I am attaching the code here.
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2026-01-25 7:57 AM - edited 2026-01-25 7:58 AM
Hi @chanchal94
Here in attached a working CubeIDE with ADC+GPDMA1+TIM3 tested on NUCLEO-N657X0-Q and generated with CubeMX.
In your code, the ADC_DMA_Buffer array, must be in the same type as GPDMA in uint32_t.
I also added RIF-Aware such as GPDMA1 and ADC12 in SystemIsolation_Config()
Then it is also safe to start ADC and DMA before TIM3.
The code is working on PA9 ADC1_INP10, PF3 ADC1_INP16 and PB10 ADC1_INP8.
Here below the results of ADC_DMA_Buffer in Live Expression in CubeIDE and the USART1 printf:
Best regards,
Romain,
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2026-01-23 1:40 AM
Hello @chanchal94
After checking main.c it seems that you do not configure the secure and privilege mode of analog GPIOs corresponding to INP8 (PB10), INP10 (PA9) and INP16 (PF3).
This must be done using the function:
HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes)
Refer to the function SystemIsolation_Config() in the examples below:
STM32Cube_FW_N6_V1.3.0\Projects\NUCLEO-N657X0-Q\Examples\ADC\ADC_MultiChannelSingleConversion
and ADC_SingleConversion_TriggerTimer_DMA
You can also refer to this similar discussion :
Re: STM32N657X0-Q ADC+TIMER+DMA - STMicroelectronics Community
Best regards,
Romain,
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2026-01-23 11:14 PM
I have configured the secure and privilege attributes of the ADC analog GPIOs (PB10, PA9, and PF3) using HAL_GPIO_ConfigPinAttributes() as suggested. However, the behavior remains unchanged, and no data is being captured on any of the three ADC channels.
I have also addressed the related security constraints as recommended. Could you please advise if there are any additional RIF-related configurations that need to be verified or enabled?
Additionally, I would like to confirm whether enabling I-Cache and/or D-Cache is required for proper ADC + DMA operation on this device.
Kindly help me in sorting this out.
Regards
Chanchal
2026-01-25 7:57 AM - edited 2026-01-25 7:58 AM
Hi @chanchal94
Here in attached a working CubeIDE with ADC+GPDMA1+TIM3 tested on NUCLEO-N657X0-Q and generated with CubeMX.
In your code, the ADC_DMA_Buffer array, must be in the same type as GPDMA in uint32_t.
I also added RIF-Aware such as GPDMA1 and ADC12 in SystemIsolation_Config()
Then it is also safe to start ADC and DMA before TIM3.
The code is working on PA9 ADC1_INP10, PF3 ADC1_INP16 and PB10 ADC1_INP8.
Here below the results of ADC_DMA_Buffer in Live Expression in CubeIDE and the USART1 printf:
Best regards,
Romain,
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2026-01-27 9:50 AM
Thank you @RomainR. for your response.