Posted on April 19, 2006 at 04:48Hello Moderaters,
I have a question about register RCCU_PLL1CR's bit6, FREF_RANGE. In specification, '1' indicates the input frequency, CLK2, should greater than 3MHZ, '0' means CLK2 from 1.5MHZ to 3MHZ.
In my test board, processor is STR710FZ2, external CK is a 4MHZ crystal, I set this bit to '1' and RCCU_CFR's bit15, div2, is reset value '1'. This means CLK2 is 2MHZ, bit 'FREF_RANGE' should be '0', the PLL1 works well. But my PLL1 works well with this bit, 'FREF_RANGE', is '1'.
Until now all good, but is there any potential problems with this kind of setting?
Could anyone answer this question?
Thanks.
Dawei
