IIS3DWB - Registers reset with STEVAL-MKI208V1K

[rti]

Hello,

I have a setup with a processing unit connected to two IMU sensors via SPI.

One of those IMU's is the IIS3DWB.

I am configuring the IIS3DWB with FIFO in continuous mode and I can read data properly from FIFO.

I decided to make long run tests. With these tests, I noticed that some times after 10 minutes, after 2h or more, I can't read data from the IIS3DWB FIFO since the values read from FIFO_STATUS1 and FIFO_STATUS2 are 0.

I wrote a piece of code to only run after this transition from proper read to read 0's, where I read the CHIP_ID and the FIFO_CTRL registers. The result is a proper read of the CHIP_ID and the all FIFO_CTRL registers are read as 0.

It looks to me that some reset occurred to the internal registers. Aren't the capacitors of the STEVAL board making his job?

As a note, the other IMU continuous working properly and SPI bus also does not present any issue.

Do you have a suggestion on how to mitigate or debug further?

Thank you.

[rti]

Hello,

I decided to conduct another test. I disabled the code that reads the FIFO_DATA_OUT_TAG(78h). I still perform the initial configuration of the sensor and FIFO and then only monitor the FIFO_STATUS1/2.

My expectation was to have a FIFO size of always 512. That happens most of the times, but some times I read a FIFO size of 0 with the bit of watermark on. The full and overrun are not constant. Also the bit 3 of FIFO_STATUS2 is in the datasheet mentioned as value 0, sometimes I read a 1 in that position.

Is this matching a behaviour expected from ST?

Also if I only read the FIFO_STATUS1/2 and never read the FIFO_DATA_OUT_TAG, I don't see any internal reset of the sensor registers.

Thank you for your support.