How to choose the right ESD protection for my design?

0. Summary

This article answers some Frequently Asked Questions about ESD protection electrical characteristics.

1. How to select the VCL? (what is the maximum transient voltage accepted by my
circuit and if I can assume the maximum absolute voltage of my ICs or is there
a better approach to follow?)

The absolute maximum rating (AMR) voltage value is not relevant because it is a DC measured voltage and not measured for a transient voltage, hence an intrinsically pessimistic value (AMR value is too low).
The best approach to select the VCL is to apply the SEED (System-Efficient ESD Design) methodology described in our ESD Webinar.
If any TLP information is available for the IC to be protected, the rule is the lower VCL, the better protection.

2. Are there any easier rules to apply to choose the key parameters?

Secure margin between AMR and maximum ESD clamping voltage before destruction can be very scattered. To select the best ESD protection, bandwidth must not be over-sized, VRM must be just slightly higher than line voltage to lower the clamping voltage.

3. I need to populate different interfaces with ESD protection, can I use the same ESD protection for all these interfaces?

Yes, but keep in mind that each interface has its own requirement. For example you may choose a low capacitance ESD in a 2-line package to protect Dplus and Dminus pins of an USB connector in order to keep the best signal integrity on these datalines whereas you may choose a single line ESD protection with high capacitance for a touch button to lower signal bouncing.

4. What is exactly the VRM parameter of an ESD protection and what is it good
for?

VRM is the maximal operating voltage of the protection to ensure a good transparency of the application voltage signal in the normal operation. The VRM of the ESD protection must be higher than the normal signal voltage amplitude. If the signal is negative and positive, the protection must be bi-directional to avoid rectifier phenomenon. If the signal to be protected is only positive, an unidirectional protection is preferred. Along with the VRM voltage there is also the protection current leakage parameter called IRM. A too high leakage current can affect the system overall consumption but it can also change a data line voltage. Usually, the leakage current is below 1 μA at VRM (ESDZV5 has IRM e.g. at 100 nA maximum).

5. What does is meant with snap-back ESD protection?

Standard ESD protections activate at breakdown voltage (called VBR) and their voltage increases with the current linearly to clamping voltage. The snap-back protection instead has a snap-back effect which means that it lowers its clamping voltage after the protection is triggered. The holding voltage (VH) is the lowest voltage when the
snap-back protection has turned on. The lower is the holding voltage, the better is the clamping voltage.
The figures below show on the left the I/V characteristics of a standard ESD protection and on the right the I/V characteristics of a snapback ESD protection.

6. When the use of TVS is not enough for protection (for example when voltage or
current is exceeded), do you recommend serial resistor or other type of
components?

Adding a serial resistor can be recommended because it will decrease the clamping voltage on protected IC I/O. But for some interfaces, adding a serial resistor may exceed the line impedance specified in the standard or decrease the bandwidth.

7. Do we need ESD for the RS-485 transceivers or is it included?

Check the ESD specification for your RS-485 transceiver: if it is only rated per HBM, then system-level ESD is needed (IEC61000-4-2). To protect RS485 transceiver, ESDA14V2BP6 is recommended.
Check the schematic in figure "ESD14V2BP6 protection device schematic" in AN5245.
ST485 transceiver can be split in 2 families:
• with system ESD protection (ST485E series)
• without system ESD protection (ST485 series)
When ST485E series cannot be placed close to the ESD source, it is required to use external ESD protections in order to avoid any EMI coupling with internal PCB tracks. EMI coupling induced by ESD can generate latch-up failures in your system.