STM32 MPUs

As defined in the title, I want to make a clean image for my stm32mp257F-DK without any graphic package. But I also want to use the Real Time layer with it (that is not supported at the moment, but I work in advance). However the RT layer depends on the meta-st-openstlinux one. But when I want to build my st-image-core, I see that there is some graphic packages that are installed. I think about libglu that make the build crash with the following error :fatal error: KHR/khrplatform.h: No such file or directory| 37 | #include <KHR/khrplatform.h> Is there a way to avoid this behaviour ? Or do I something wrong ? Here is my bblayers.conf :# POKY_BBLAYERS_CONF_VERSION is increased each time build/conf/bblayers.conf# changes incompatiblyPOKY_BBLAYERS_CONF_VERSION = "2"BBPATH = "${TOPDIR}"BBFILES ?= ""LAYERS_REPO = "${TOPDIR}/../layers"BBLAYERS ?= " \  ${LAYERS_REPO}/poky/meta \  ${LAYERS_REPO}/poky/meta-poky \  ${LAYERS_REPO}/poky/meta-yocto-bsp \&nbs

Hi Team,I am able to test FDCAN1 on M33 core of STM32MP257F EV1 board, using STM32Cube\Repository\STM32Cube_FW_MP2_V1.1.0\Projects\STM32MP257F-EV1\Examples\FDCAN\FDCAN_Com_IT and PEAK PCAN Usb. However, when I try to change the same code to work for FDCAN2, I couldn't achieve it. as A35 core is going to reset, probably due to wrong call to Resource Manager. Below is the snippet of code used. /* Acquire FDCAN using Resource manager */if (RESMGR_STATUS_ACCESS_OK == ResMgr_Request(RESMGR_RESOURCE_RIFSC, STM32MP25_RIFSC_FDCAN_ID)){/* Enable FDCANx clock */FDCANx_CLK_ENABLE();} /* Acquire GPIOJ14 using Resource manager */if (RESMGR_STATUS_ACCESS_OK != ResMgr_Request(RESMGR_RESOURCE_RIF_GPIOJ, RESMGR_GPIO_PIN(14))){Error_Handler();} /* Acquire GPIOI12 using Resource manager */if (RESMGR_STATUS_ACCESS_OK != ResMgr_Request(RESMGR_RESOURCE_RIF_GPIOI, RESMGR_GPIO_PIN(12))){Error_Handler();} /* Enable GPIOs power supplies */if (RESMGR_STATUS_ACCESS_OK == ResMgr_Request(RE

We are pleased to announce that STM32CubeProgrammer 2.20 is available What is new in 2.20: • Support for the STM32MP21x microprocessors:         – External memory programming        – OTP programming        – PKCS#11        – ST power management IC• Support for MCE Noekeon encryption for STM32N6 series microcontrollers• Extended PMIC support to more components• Support of the Secure Manager on external flash memory for STM32H573xx microcontrollers• Recovery button for STM32H5 series microcontrollers• Support for Chinese and Japanese languages• Support for incremental programming for STM32WB5xxx/35xx and STM32G0B0xx/B1xx/C1xxmicrocontrollers• Support for macOS® on Apple® silicon Main fixed issues in 2.20: Refer to the STM32CubeProgrammer wiki at: STM32CubeProgrammer errata 2.20.x - stm32mcu Known problems and limitations in 2.20: Refer to the STM32CubeProgrammer wiki at: STM32CubeProgrammer errata

I am running bitbake core-image-minimal;The build error is as followsERROR: mesa-2_24.0.7-r0 do_configure: meson failed ERROR: mesa-2_24.0.7-r0 do_configure: ExecutionError('/home/l/yocto/build/tmp-glibc/work/cortexa7t2hf-neon-vfpv4-oe-linux-gnueabi/mesa/24.0.7/temp/run.do_configure.1438955', 1, None, None) ERROR: Logfile of failure stored in: /home/l/yocto/build/tmp-glibc/work/cortexa7t2hf-neon-vfpv4-oe-linux-gnueabi/mesa/24.0.7/temp/log.do_configure.1438955 Log data follows: | DEBUG: Executing python function extend_recipe_sysroot | NOTE: Direct dependencies are ['/home/l/yocto/layers/openembedded-core/meta/recipes-core/expat/expat_2.6.2.bb:do_populate_sysroot', '/home/l/yocto/layers/openembedded-core/meta/recipes-core/glibc/glibc_2.39.bb:do_populate_sysroot', '/home/l/yocto/layers/openembedded-core/meta/recipes-core/zlib/zlib_1.3.1.bb:do_populate_sysroot', '/home/l/yocto/layers/openembedded-core/meta/recipes-devtools/gcc/gcc-cross_13.3.bb:do_populate_sysroot', '/home/l/yocto/layers/

Hi everyone, I have the stm32mp257f-ev1 st-image-weston build./sources/tmp-glibc/deploy/images/stm32mp25-eval/flashlayout_st-image-weston/optee ├── FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-optee.tsv ├── FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsv ├── FlashLayout_emmc_stm32mp257f-ev1-optee.tsv ├── FlashLayout_nor-sdcard_stm32mp257f-ev1-optee.tsv ├── FlashLayout_sdcard_stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-optee.tsv ├── FlashLayout_sdcard_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsv └── FlashLayout_sdcard_stm32mp257f-ev1-optee.tsvI have NOR woth SDCard boot, but how can i boot from NOR and EMMC, i dont see any .tsv file here.And i don't know the boot switch for this. please help me in creating a tsv file and understanding the boot switch configuration. 

Hi Everyone,I'm trying to understand the NOR Flash boot sequence of stm32mp257f-ev1. Im using generated FlashLayout_nor-sdcard_stm32mp257f-ev1-optee.tsv to flash the st-image-weston image.I want to understand how exactly the boot sequence is started and how it reaches to the u-boot (normal-world boot). I had a pre-work in understanding this boot sequence, I need a clarification on my understandingThe stm32mp2 boards follow arm trusted boot chain. That means TF-A and OPtee will be the FSBL and U-boot will be SSBL. So during the power on cycle the ROM code initiates the OCTOSPI interface of the Processor in Legacy SPI (MOSI and MISO) mode at HSI/2 = 32MHz speed. Then is loads the Initial DT + BL2(optee) to SRAM and initialise the CPU clock and DDR.Once the CPU is initialised, based on the arm-firmware SPI_NOR and SPI_MEM framework and the boot_device.c configuration, the OCTO SPI is configured to QUADSPI in 1-1-4 (QREAD) mode at max speed (133MHz) speed and

I'm working with the STM32MP257F-DK board and using the NXP IW612 wireless module, which is connected through the Murata uSD-M.2 adapter via the board's microSD card slot.When I connect the adapter, the mmc interface detects it in high-speed mode, with a clock frequency of 50 MHz and a signal voltage of 3.3 V.To cross-check, I connected a standard SD card to the same slot, and it was correctly detected in UHS mode with a 100 MHz clock and 1.8 V signal voltage.I want the Murata adapter (with IW612) to operate in UHS mode, using: A higher clock frequency (e.g., 100 MHz or above)1.8 V signaling (switch from default 3.3 V)What steps are required to achieve this? Do I need to modify the Device Tree(DTB)? Are any voltage regulators or GPIO controls required to enable the 1.8 V switch? What are the minimum hardware/software dependencies to ensure UHS mode is enabled for the SDIO interface used by the IW612?

I recently purchased the STM32MP157F-EV1 board and would like to run a Qt application on it. However, I am unfamiliar with the setup process and would appreciate your guidance on how to get started from scratch.Could you please provide me with the necessary steps, documentation, or any resources that would help me successfully deploy a Qt application on this board?I appreciate your time and support, and I look forward to your response.

Hello,My aim is to install OpenCV and use it's functionalities on STM32MP1 board. But I coulnd't find a proper documentation about it. Could you help me with this?Thanks.

I generated the M33 code using CubeIDE by following the lab manual.During the driver initializations:MX_ADC1_Init();MX_I2C1_Init();MX_ICACHE_Init();MX_RTC_Init();The A35 halts CPU1 and resets after sometime.E/TC:0 stm32_iac_itr:192 IAC exceptions [159:128]: 0x10000000E/TC:0 stm32_iac_itr:197 IAC exception ID: 156E/TC:0 Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/drivers/firewall/stm32_iac.c:212 <stm32_iac_itr>E/TC:0 TEE load address @ 0x82000000E/TC:0 Call stack:E/TC:0 0x82007ed8E/TC:0 0x82041b44E/TC:0 0x8202c2c0E/TC:0 0x8203f678E/TC:0 0x82013cf4E/TC:0 0x820017dcI/TC: Halting CPU 1Unfortunately I failed to create astable functional M33 for my MPU project yet. Are there no proper manual of code generation and configuration?

Dear Team,Is there any example code for Ethernet that works on M33 core of STM32MP257F EV1 board? Best Regards,Venkata

NOTICE: CPU: STM32MP135F Rev.YNOTICE: Model: STMicroelectronics STM32MP135F-DK STM32CubeMX board - openstlinux-6.1-yocto-mickledore-mp1-v23.06.21NOTICE: BL2: v2.8-stm32mp1-r1.0(release):custom()NOTICE: BL2: Built : 15:38:01, Jul 2 2025NOTICE: BL2: Booting BL32I/TC: Early console on UART#4I/TC:I/TC: Embedded DTB foundI/TC: OP-TEE version: Unknown_3.19 (gcc version 12.2.0 (Buildroot 2021.11-4428-g6b6741b)) #1 Wed Jul 2 06:15:25 UTC 2025 armI/TC: WARNING: This OP-TEE configuration might be insecure!I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.htmlI/TC: Primary CPU initializingI/TC: WARNING: All debug access are allowedI/TC: Platform stm32mp1: flavor PLATFORM_FLAVOR - DT stm32mp135f-dk-mx.dtsI/TC: DTB enables console (non-secure)▒_▒▒z`@`@▒▒ÿ▒▒▒▒▒▒▒▒▒▒▒zc`x@▒▒▒]▒▒▒▒▒▒▒▒▒▒▒@▒▒▒▒@▒▒▒@▒▒@▒▒▒▒▒z@xeeyybcb@\@▒▒▒▒@bac▒_▒▒z`@`@▒▒ÿ▒▒▒▒▒▒▒▒▒▒▒zc`x@▒▒▒]▒▒▒▒▒▒▒▒▒▒▒@▒▒▒▒@▒▒▒@▒▒@▒▒▒▒▒z@efdga`d@\@▒▒▒▒@a`c▒_▒▒z@▒▒▒▒▒▒▒@▒▒▒@▒▒▒▒▒▒▒▒▒@▒▒@▒▒▒▒▒▒@▒▒▒▒▒@▒▒▒▒

Hi everyone,I'm working with the STM32MP157C-DK2 board and trying to reduce the amount of RAM allocated to OP-TEE, but so far I haven't been successful.There are 32MiB DDR dedicated for OP-TEE. 30MiB for TZSRAM and 2MiB for SHMEM.In OP-TEE sources I changed value for CFG_TZDRAM_SIZE to 16 MiB and I'm keeping the value for SHMEM.In TF-a sources I changed value for DDR_SEC_SIZE to 16MiB.In Device tree I changed total RAM dedicated for OP-TEE to 18MiB.But when kernel start I have a fail: Starting kernel ... E/TC:0 E/TC:0 Core data-abort at address 0x2fff8762 (translation fault) E/TC:0 fsr 0x00000207 ttbr0 0x2ffe0000 ttbr1 0x00000000 cidr 0x0 E/TC:0 cpu #0 cpsr 0x600001f3 E/TC:0 r0 0x2fff8762 r4 0x2ffe1f71 r8 0x00000073 r12 0xe0000000 E/TC:0 r1 0x2ffe1f1c r5 0x00000000 r9 0x00000000 sp 0x2ffe1e70 E/TC:0 r2 0x2ffd3355 r6 0x00000000 r10 0x2fff8762 lr 0x2ffcdf77 E/TC:0 r3 0x2fff8762 r7 0x2ffe1f71 r11 0x2ffe1f58 pc 0x2ffcd8f8 E/TC:0 TEE load address @ 0x2ffc0000

I've been working on this for a few days now, I can't seem to get the DAC to work with the DMA. I can get the DMA to work with ADC easily, I can use the DAC without DMA easily, but the DAC doesn't feel like working with the DMA. I set up the DMA to work with the DAC channel 1 using DMA1 channel 3. I set up the interrupt to be timer 6. My code for setting things up is HAL_TIM_Base_Start(&htim6);HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, (uint32_t*) &dma_buffer, 2*DMA_BUFFER_SIZE, DAC_ALIGN_12B_R); This code is put outside of the while loop in the main function. I also checked for error codes using  uint32_t result = HAL_DAC_GetError(&hdac1); anduint32_t result = HAL_DMA_GetError(&hdma_dac_ch1); which both returned 0 in the result when debugging. I put an incrementing variable in the half and fullcomplete callbacks for debugging as well, and these interrupts appear to never fire because the variablesnever increment. I followed a guide on setting

I'm trying to get PySide6 and some common Python packages on my STM32MP257. "apt-get install python3-PySide6" doesn't work. I also tried to install the PySide6 package using pip3, which installed successfully, but gave me the error "ImportError: libX11.so.6: cannot open shared object file: No such file or directory" when I actually ran it. It seems to be missing some dependencies to support the Qt and GUI development I want to do. At this point, I'm stuck. I am using the STM32MP257F-DK development kit.

Hi, I'm new of linux.Now I have two network interface on my board, end0 for ethernet & en1u2i4 for 4G modem.The ethenet(end0) is directly connected to my PC only for development that I can use ssh to connect my board.And I want the other connection transfered by 4G modem(en1u2i4), so I use "route del default" to delete the first rule of the routing table. That will work. But I need to do this everytime the board boot up.Are there settings can be modified in the system? Or should I write a script to do "route del" command with a startup service?Thank you.

I am able to use FDCAN1 to communicate on the A7 by adding the following to `STM32MPU-Ecosystem-v6.0.0/Developer-Package/stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06/sources/arm-ostl-linux-gnueabi/linux-stm32mp-6.6.48-stm32mp-r1-r0/linux-6.6.48/arch/arm/boot/dts/st/stm32mp157f-dk2.dts`:&m_can1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_b>; pinctrl-1 = <&m_can1_sleep_pins_b>; clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; status = "okay"; };  I'd like to allocate this can device to the M4 and use the example `STM32Cube_FW_MP1_V1.7.0/Projects/STM32MP157C-DK2/Examples/FDCAN`I need help is fixing this code to get a bitrate of 1Mbps and dbitrate of 2Mbps. static void MX_FDCAN1_Init(void) { /* USER CODE BEGIN FDCAN1_Init 0 */ /* USER CODE END FDCAN1_Init 0 */ /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */ hfdcan1.Instance = FDCAN1; hfdcan1.Init.FrameFormat = FDCAN_FRA

Hello. Could someone clarify for me where this message is coming from and how can I fix it?stm32_etzpc bus@5c007000: rng@54003000 not allowed on bus (-13)Is it OP-TEE or U-Boot miss-configuration?I'm trying to patch openstlinux-6.6 OP-TEE and U-Boot for the STM32MP157C Odyssey based on the https://github.com/Seeed-Studio/meta-st-odysseyThis is my boot log:NOTICE: CPU: STM32MP157CAC Rev.Z NOTICE: Model: Seeed Studio Odyssey-STM32MP157C Board NOTICE: BL2: v2.10-stm32mp1-r1.0(release):v2.10-stm32mp-r1.2-dirty(cfe4a020) NOTICE: BL2: Built : 08:41:18, Jun 30 2025 NOTICE: BL2: Booting BL32 I/TC: Early console on UART#4 I/TC: I/TC: Embedded DTB found I/TC: OP-TEE version: 4.0.0-stm32mp-r1.2-dev (gcc version 13.3.0 (GCC)) #1 Mon Jun 30 08:40:36 UTC 2025 arm I/TC: WARNING: This OP-TEE configuration might be insecure! I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html I/TC: Primary CPU initializing I/TC: WARNING: All debug accesses are a

Hi,I am working on optimizing the boot process on my STM32MP157DAC board by removing U-Boot and booting the Linux kernel directly. I’ve been following the documented procedure from ST for the STM32MP1 series:ST Wiki - How to optimize the boot timeTF-A ConfigurationI’ve updated the configuration in stm32mp1_def.h as follows:#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x2008000))#define STM32MP_BL33_MAX_SIZE U(0x3FF8000)SD Card Timeout ModificationModified the SD card timeout value in <tf-a_sources>/drivers/st/mmc/stm32_sdmmc2.c:timeout = timeout_init_us(TIMEOUT_US_1_S * 10);TF-A Build Process:I applied the changes as a patch through my custom Yocto layer and rebuilt the tf-a-stm32mp recipe successfully.Kernel Configuration:I added the following configuration parameters to my stm32_defconfig:CONFIG_CMDLINE_BOOL=yCONFIG_CMDLINE="root=PARTUUID=e91c4e10-16e6-4c0e-bd0e-77becf4a3582 rootwait rw earlyprintk earlycon console=ttySTM0,115200"I created and applied a patch

Hi STM Team,We are working with a custom board based on the STM32MP157DAC.We are facing a video lag issue when trying to play a video file from Qt application 6.5.3 using media player.Even reducing the frame rate had no effect.But if we use gst-play we are able to play the video without any lag or delay.Do we need to enable any HW accelerator to play the video over GPU from Qt application? how we achive the same video output without lag when played using gst-play from Qt application.Thanks.

Hi everyone,I'm attempting to optimize the boot process on my STM32MP157F-DK2 board by removing U-Boot and booting the Linux kernel directly via the FIP. I've followed the documented steps for STM32MP1:TF-A BL2 Modifications:Updated STM32MP_BL33_BASE and STM32MP_BL33_MAX_SIZE in the STM32MP1 header file.Increased the SDMMC timeout in stm32_sdmmc2.c to accommodate the larger kernel image.FIP Creation:Recompiled TF-A with my modifications.Created a new FIP where I replaced the U-Boot binary and its DTB with my Linux kernel Image and DTB.The new FIP (fip.bin) now contains the kernel and DTB.Flash Layout TSV Modifications:I updated the TSV file to allocate a larger space for the FIP. Below is the relevant excerpt:Despite these modifications, every time I execute the process, it fails. My questions are:What is the purpose of the bootfs partition?Since my new FIP (fip.bin) already contains the Linux kernel and its DTB, I'm unclear why the flash layout still reserves a bootfs partition. Is it

Hello,I'm using Buildroot environment with the STM32MP257F-DK board. I'm testing GStreamer with a simple pipeline:gst-launch-1.0 videotestsrc ! autovideosinkWhen I first run it there is no problem. The test video shows fine on the HDMI monitor. But when I run it again second time there are errors : pipeline doesn't want to preroll. And all attempts after that fail too. It works only one time after the boot.There is additional debug info: drmModeSetPlane failed: No space left on device (28).Maybe some setting is missing ?BRraimo

I am using a custom board (STM32MP157DAA1) and want to use DSI 1 lane. How do I set it up in uboot or kernel?My screen also has 1 lane.

I've been playing with the STM32MP257-DK, first looking at the start package. I have now delved further with the developer package, and ran into issues while following the README.HOW_TO.txt that is found in the linux kernel directory. I followed the directions exactly, and created the filesystem structure as shown in ST documents. But when I run this line below, I get failures. It seems the external device tree does not have a .dtb file. When Iook at what is present in the external device tree directory it only contains .dts files, but NO .dtb files. The previous instructions place the .dtb files in the following locations. The error seems to be in the <name of external devicetree .dtb> argument.  I tried pointing it to the install_artifact/boot but that does not fix the issues even though there are .dtb files there since MAKE looks for the .dtb files specifically in the KBUILD_EXTDTS="${EXTDT_DIR}/linux" argument. I also tried pointing it to the build/arch/ar

Hi !I am designing a SOM board (based on MP2 microprocessor) and I'm wondering if I must take into account the die-to-pin lengths on LPDDR4 IC side. Or does the intrisic architecture of LPDDR4 components garantee internal equivalent lengths ? I didn't find any related information on LPDDR4 IC manufacturer website, and there isn't much support.I've allready taken into account lengths on MP2 side.Thank you, have a nice dayBest regardsNicolas