STM32 MPUs

HelloI detect (regular) ST-LINK v32 with STM2CubeProgrammer, but it remains not connectrd.Please tell me what is the problem and how to fix this problem. ?［LOG］18:18:10 : STM32CubeProgrammer API v2.14.0 | Windows-32Bits18:18:13 : UR connection mode is defined with the HWrst reset mode18:18:13 : ST-LINK SN : 002800205553500E2039325618:18:13 : ST-LINK FW : V3J12M3B5S118:18:13 : Board : STLINK-V3SET18:18:13 : Voltage : 3.33V18:18:13 : SWD freq : 8000 KHz18:18:13 : Connect mode: Normal18:18:13 : Reset mode : Hardware reset18:18:13 : Device ID : 0x50018:18:13 : Revision ID : Rev Z

I want to emulate the stm32mp157 on qemu. I have been taking the kernel image and initrd from yocto build, but it is not loading the kernel. using the following commandqemu-system-arm \-M virt -smp 8,sockets=1,cores=4,threads=2 -m 4G \-cpu cortex-a7 \-device virtio-tablet-pci \-device virtio-keyboard-pci \-device virtio-net-pci,netdev=net0,mac=52:54:00:12:34:02 \-device virtio-gpu-pci \-device virtio-rng-pci,rng=rng0 \-netdev tap,id=net0,ifname=$TAP,script=no,downscript=no \-object rng-random,filename=/dev/urandom,id=rng0 \-serial mon:stdio -serial null -nographic \-initrd senecos-image-stm32mp1-ems-c2-faa1-20230803140050.rootfs.cpio.gz \-kernel Image \-append 'root=/dev/ram0 rw debugshell ip=192.168.7.2::192.168.7.1:255.255.255.0::eth0:off:8.8.8.8 console=ttyAMA0 console=hvc0 '

Hello,I would like to ask you few questions since I have some unclearances about STM32MP157F MPU:1. If 933MHz DDR3L RAM was connected to the MPU according to the schematic, will the MPU automatically underclock it to max 533MHz?2. Is it possible to connect an OLED display to the STM32MP157F?3. Since SLC NAND memories are quite expensive in higher densities (>= 16GB), would it be a problem if a different configuration  such as TLC was used? Does the cell configuration also matter in e.MMC and what is its max data transfer rate for read/write when connected to SDMMC, if the datasheet says max I/O speed is 208 MB/s? Would it be possible to use HS200 mode to take advantage of the maximum capabilities of the MPU?4. If the Wi-Fi + Bluetooth module has a Wi-Fi SDIO host interface and as stated , the SDMMC supports data rates up to 208 MB/s, would it be possible to use the Wi-Fi 5/6 module to also take advantage of the MPU maximum capabilities instead of the Wi-Fi 4 65Mb/s (8,125MB/s)

Recently I got a problem with RPMSG driver when M5 coprocessor restarts. Thanks to https://community.st.com/s/question/0D53W00000936uRSAQ/kernel-panic-with-pollselect-syscalls-on-virtual-uart-devices-to-m4-core-when-m4-watchdog-restarts?t=1632144260162the problem is over.Now I get the same problem with RPMSG SDB driver (see attachment). Can you help me ?

I am working on yocto project. I started with a custom board based on stm32mp157. You can find the board description in this link custom board. Vendor has a board support package in dunfell version. But I am doing my project in kirkstone version. I have choosen my distribution packgae from the openstlinuxdistribution. I have following build configuration for creating the image:Build Configuration: BB_VERSION = "2.0.0" BUILD_SYS = "x86_64-linux" NATIVELSBSTRING = "universal" TARGET_SYS = "arm-emt_eglfs-linux-gnueabi" MACHINE = "emsbc-argon" DISTRO = "emt-eglfs" DISTRO_VERSION = "1.3" TUNE_FEATURES = "arm vfp cortexa7 neon vfpv4 thumb callconvention-hard" TARGET_FPU = "hard" DISTRO_CODENAME = "kirkstone" ACCEPT_EULA_emsbc-argon = "1" GCCVERSION = "11.%" PREFERRED_PROVIDER_virtual/kernel = "linux-stm32mp-argon" meta-emtrion-emsbc-argon meta-emtrion = "<unknown>:<unknown>" meta = "HEAD:f7766da462905ec67bf549d46b8017be36cd5b2a" meta-oe meta-initramfs meta-multimedia me

Hi,I'm having some difficulty routing 1GB DDR3L memory with the STM32MP151DAC1. Both reference boards available for this product use different memory or pitch configurations. I found an Application Note, AN5122, that guides through memory routing, but I would like some actual reference design example, to compare. There are any reference, ap notes, or anything to help with this?Regards,Arion Doneda

Hi,I find the 'STM32MP1_SeriesDDRmemory_routing_guidelines_layout_examples_V3.0' from ST's site.I've several questions: It seems the column 'STM32MP15XXAA LENGTH (mm)' is the package delay per pin, right?Actually, the delay is a time factor. But here the delay is given in 'mm', then what's the propagation speed ST used?Can you provide delays in ps? Or can I get the delays from the IBIS file?Thanks.

Hi,Are there any references for configuring the I2S supply voltages in device trees for STM32MP135-DK.From the I2S module currently we are getting the output level as 5V, is that expected or is there any way to change that from 5V to 3.3V.

Hi,After reading the document I understand the interrupts are handled by pin#, and we set GPIOsel within EXTI_ConfigTypeDef.My question is how do we determine which port generates the interrupt?Suppose I use PA0 and PB0, and I only want to use one callback function for them.void callback(){ if(port == GPIOA) { do something } else if(port == GPIOB) { do other thing }}Thank you

Hello!I am using the CortexM4 coprocesor on the STM32MP157F-DK2 to measure multiple ADC channels and update a control loop based on the values. I have set up ADC1 using the DMA2 in circular mode to read channels IN1, IN2, and IN4. I have a buffer set up in which I place the values of the ADC. I also have a timer running so that upon the timer event, the ADC conversion is trigger. ADC1 is set up so that IN1, IN2, and IN4 have rank 1, rank2, and rank3 respectively. The problem I am facing is that each time I restart the DMA(firmware restart), it changes the index of the DMA buffer for each ADC channel. So for example, during testing, I have IN1 connected to 3.3V, IN2 connected to 0V and IN4 connected to 1.65V.The first time I stop the DMA and read the buffer I see these values.This makes sense because the first channel should be highest, second channel should be around 0, and third channel should be about half the first channel. However, after running my code and stop/start the DMA multi

Hello,We are using STM32157AAA3 Processor in our custom board.we are trying to ping ethernet in RMII (100mbps)mode  in uboot (2023.04) version.we are  facing following issues :1. Invalid PHY Interface.2. eqos_probe_failed() -22 No ethernet found  (as in below screenshot). when we try to ping ethernet in RGMII Mode with auto negotiation  we are getting Host is not alive.But in uboot 2018 version it is working fine in RMII (100mbps).Please find the below attached screen shots for configuration,what we have done  for ethernet in uboot-2023V.please help us in this regards.regards,Navaneeth kumar 

Hi Community,I realise that this may be a very newbie question:I have run all the steps as seen on the Wiki,I followed these steps to the letter: https://wiki.st.com/stm32mpu/wiki/PC_prerequisitesFolowed by:mkdir -p st/buildcd st/buildrepo init -u https://github.com/STMicroelectronics/oe-manifest.git -b refs/tags/openstlinux-6.1-yocto-mickledore-mp1-v23.06.21repo sync DISTRO=openstlinux-weston MACHINE=stm32mp15-disco source layers/meta-st/scripts/envsetup.shbitbake st-example-image-qtwaylandAll these steps were completed successfully :heavy_check_mark:I'm looking at the tmp-glibc/deploy/images/stm32mp15-disco/ directory and I am unable to figure out which of these I need to flash on to the SD card using etcher on my PC.Could someone help point me in the right direction?Thanks,

Hello, I am currently researching about possibilities in STM32MP1 dual core. I am trying to create user program that uses HW Semaphore. On M4 side is everything clear. But I cannot create program for A7 core. Here is what I think that I suppose to do:- create user program with hwspinlock.h- build corresponding version of linux kernel- include kernel files to makefile.But when I try to make my custom program, i got much errors from kernel source tree.For me, how to properly include hwspinlock framework is not clear from ST wiki or hwspinlock framework documentation.Thanks for any response.

1、Part Number：STM32MP135FAE7 2、tzc_it_handler:72 TZC permission failure3、Environment：PC：ubuntu18，environment-setup-cortexa7t2hf-neon-vfpv4-ostl-linux-gnueabi，arm-ostl-linux-gnueabi4、We designed a STM32MP135 based SOM, using the ST I2C PMIC, STPMIC1D，1GiB DDR3L。5、At present, after the modification of TF-A,OP-TEE device tree, TZC panic occurred when downloading, now check U-boot device tree, I do not know where to find the cause.6、Attached is the log printed by uart4 debug

Hi,I'm searching any information about how exclusive access (LDREX / STREX instructions) is implemented in STM32MP157 silicon. Unfortunately, it seems that ST assumes that this information is obvious.Based on ARM documentation, the synchronization is either provided by the SCU or the memory shall be marked Shareable (see https://developer.arm.com/documentation/dht0008/a/arm-synchronization-primitives/exclusive-accesses/use-in-multi-core-systems).Based on the STM32MP157 datasheet, figure 1: the SCU unit is part of the Level-2 cache connected to the dual-A7. However, the M4 core is on another bus. So I suppose that the SCU will not ensure A7 <-> M4 exclusive access.The other option is Sharable memory. So the question is: is functionality of ldrex/strex instructions between A7 and M4 cores guaranteed when the memory is marked as Shareable in MMU / MPU?Based on another articles, the behavior of Sharable memory depends on implementation of bus, bus interconnec

Greetings,  I have a few STM32MP1 boards. One of which I have configures the OS on, and custom applications.I copied the SD card and put it in another one.  The MAC address is the same. I read an STM article about the MAC address and "fuse sense 0 57 2" shows me the correct MAC address.  So it must be in software somewhere.  Where?

I built my image to test flutter gallery application from meta-flutter/workflows/stm32mp15. My local.conf file can be seen below:ACCEPT_EULA_stm32mp15-disco = "1" IMAGE_LINGUAS = "en-us" TOOLCHAIN_HOST_TASK:append = " nativesdk-flutter-sdk" CLANGSDK = "1" DISTRO_FEATURES:remove = " x11 " PACKAGECONFIG:pn-flutter-auto-runtimerelease = "backend-egl mouse-cursor package-info secure-storage text-input texture-test-egl" IMAGE_INSTALL:remove = " packagegroup-st-demo " IMAGE_INSTALL:remove = " gtk+3-demo " IMAGE_ROOTFS_MAXSIZE = "3145728" IMAGE_INSTALL:append = " flutter-auto-runtimerelease flutter-engine-runtimerelease-sdk-dev flutter-gallery-runtimerelease flutter-test-video-player-runtimerelease adwaita-icon-theme-cursors xdg-user-dirs avahi-daemon ntp ntp-tickadj gstreamer1.0-libav gstreamer1.0-plugins-bad gstreamer1.0-plugins-good gstreamer1.0-plugins-ugly" LICENSE_FLAGS_ACCEPTED += " commercial" I flashed the image and in the home/root path there is a README file it says:Check GPU =====

Hi,I encounter a performance issue on the qt5 application on STM32MP135. I build a simple application with three plaintextedit objects showing temperature with 1s period from ds18b20. Everything compiles well and works, but the refreshing temperature on plaintextedit consumes 80% of the CPU (only refreshing after that go to 10% or less)Maybe someone has a similar problem to my. The same application on STM32MP157 works perfectly response on the screen and consumes only 10 to 20% in peak on CPU load. In my opinion, something is wrong with the compilation optionsI built it like for STM32MP157 without accepting EULA (this model has no graphics on board). bitbake -k st-example-image-qt -c populate_sdk bitbake -k st-example-image-qt  Thanks for any hintsBRMichal

Hi,We are currently working on a project that involves utilizing the STM32MP13X MPU. Our device operates in both ACM and Mass Storage Mode, and we would like to inquire about the process of obtaining a custom name for the virtual serial COM port generated by the STM32MP13X when connected via USB.Specifically, we would like to understand the steps involved in acquiring a custom name for the virtual serial COM port and also a new product ID. We got know that ST offers sub-licensing for this instead of getting a vendor ID from usb.orgAny guidance on how we can get a distinct name? We aim to have a distinct name for our COM port to enhance the user experience and differentiate our product in the market.

Hi,I like to use spidev_test tool:https://wiki.st.com/stm32mpu/wiki/How_to_use_SPI_from_Linux_userland_with_spidev#Installation_on_your_targetI am following this guide for compiling the tool by developer package:https://wiki.st.com/stm32mpu/wiki/How_to_build_Linux_kernel_user_space_toolsThese are commands I have used: cd ~/Distribution-Package/openstlinux-5.10-dunfell-mp1-21-03-31/build-openstlinuxweston-stm32mp157a-visionsom-hdmi-emmc-mx/tmp-glibc/deploy/sdk ./st-image-weston-openstlinux-weston-stm32mp157a-visionsom-hdmi-emmc-mx-x86_64-toolchain-3.1-snapshot.sh . /opt/st/stm32mp157a-visionsom-hdmi-emmc-mx/3.1-snapshot/environment-setup-cortexa7t2hf-neon-vfpv4-ostl-linux-gnueabi cd ~/Developer-Package tar xfJ en.SOURCES-stm32mp1-openstlinux-5.10-dunfell-mp1-21-11-17_tar.xz cd stm32mp1-openstlinux-5.10-dunfell-mp1-21-11-17/sources/arm-ostl-linux-gnueabi/linux-stm32mp-5.10.61-stm32mp-r2-r0 tar xfJ linux-5.10.61.tar.xz cd linux-5.10.61 for p in `ls -1 ../*.patch`; do patch -

First I declare the buffer length/* USER CODE BEGIN PD */ #define ADC_BUF_LEN 10000Then I declare the buffer/* USER CODE BEGIN PV */ GPIO_InitTypeDef gpio_init_structure; VIRT_UART_HandleTypeDef huart0; VIRT_UART_HandleTypeDef huart1; uint16_t adc_buf[ADC_BUF_LEN];I've enabled the VREF/* USER CODE BEGIN 2 */ // Enable the VREF clock __HAL_RCC_VREF_CLK_ENABLE(); // Disable the high impedance mode which is the default one read page 1694 of refman HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE); HAL_SYSCFG_VREFBUF_VoltageScalingConfig(SYSCFG_VREFBUF_VOLTAGE_SCALE2); // To enable VREFBUF HAL_SYSCFG_EnableVREFBUF();Finally I start the ADC over DMAHAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buf, ADC_BUF_LEN);I seem to get reasonable values when in engineering mode and look at variables in debug mode, however, when I build for release, then scp the file to the Linux core, then use the fw_cortex_m4.sh to forward the elf file, I get values of 4095.0000 every time

Hi,Is it possible to utilize the PCM1754 DAC as a Sound card with the ALSA Framework on OpenSTLinux?According to the documentation, the PCM1754 functions as a Hardware-controlled DAC, eliminating the need for additional drivers. Therefore, is it necessary to develop custom drivers for this particular DAC if we are using linux as OS?If it is possible, are there any references for configuring device tree files and sound card configuration to facilitate this setup? 

Hello everyone! I am working on a small prototype based on the STM32MP157F-DK2 development board. For convenience, I want to use a GPIO Connector compatible with the Raspberry Pi to power the board (CN2) instead of the USB Type-C (CN6). I have an expansion module that successfully powers the Raspberry Pi through the GPIO connector (pin 2, 4), but it cannot provide power to the STM32MP157F-DK2 board. The kernel doesn't start up, and an error message appears, indicating the lack of proper power and suggesting the use of power supplies with a 3A current. My module can provide up to 3 amps, which is equivalent to the output of my power adapter that I use to supply power to the board via USB Type-C. I even conducted an experiment and routed the power from the expansion module to the USB Type-C connector (CN6), successfully powering the board, which indicates that the power source is working correctly. Is it possible to power the STM32MP157F-DK2 board through the GPIO connector? If yes, what

We are experiencing an issue where, in approximately 1 in 1000 cases, we don't get a TxRxCpltCallback callback after starting a SPI DMA transfer from an ISR on the ARM-M4 (coprocessor). The transfer appears to have taken place as all the bytes are received in the Rx data buffer, and scope traces show the SPI transaction occurred successfully. However afterwards, whilst `hspi->hdmatx->State` is the expected `HAL_DMA_STATE_READY`, `hspi->hdmarx->State` is still `HAL_DMA_STATE_BUSY`.To be clear, the vast majority of the time, it is working as expected, but it appears to be some kind of race condition where occasionally, the completion interrupt doesn't occur.The use case is for reading a set of samples (18 bytes) from a multichannel ADC. An interrupt "data ready" is given, and we are using the `HAL_SPI_TransmitReceive_DMA()` function inside this minimal ISR. I've done quite a bit of profiling for this case, so I am confident we exit the ISR well before the SPI transaction has

Dear ST team, Hope you're doing well.We have developed a custom board based on STM32MP151 with emmc. Currently, we are using STM32MP151 for  flashing. The problem is each flash is taking around 15 minutes time and it will be a critical issue in our production cycle because we will produce the boards in large quantities.Please give your valuable advice on the below queries.1. Can we reduce the flashing time?2. Can we flash multiple boards in parallel?