STM32 MPUs

I am trying to debug a project I have created in STM32CubeMX and edited in STM32CubeIDE with the STM32MP257F-DK. I am seeing an intermittent error which is mentioned in the troubleshooting grid, but it's not clear to me how to fix it.  After it builds with no errors, I get a familiar message:Error in final launch sequence:Failed pre launchFailed pre launchFirmware remoteproc load failed, please:1. make sure that /lib/firmware on your target has space2. make sure that /lib/firmware has write access> you can open a Console View for this..When I check dmesg on the board, I see the lines[ 58.546876] remoteproc remoteproc0: powering up m0[ 58.628708] remoteproc remoteproc0: Booting fw image Project_Name_CM33.elf, size 3097880[ 58.631958] remoteproc remoteproc0: bad phdr da 0x80100000 mem 0x540[ 58.638236] remoteproc remoteproc0: Failed to load program segments: -22[ 58.645251] remoteproc remoteproc0: Boot failed: -22This "bad phdr" line is mentioned in Table 1 of the troublesho

Greetings,We're developing our product on our MYIR MYC-LD25X SoM based on the STM32MP257DAK3 MPU with 8GB eMMC non-volatile storage.As per our design requirements, I am required to enforce the STM32 MCU Equivalent of CRP Level 1 or 2 on our Non-Volatile storage so that once we have flashed the eMMC with our program, It's content could only be read/written by the program flashed onto the eMMC & not by JTAG, SWD, etc methods.Using an eMMC chip that provides these protection might be an option but is it atleast possible to enforce write protection using the MPU itself? For example the MPU could have a small program running which could then verify if the contents of the eMMC were tampered with?Regards,Aditya M.

Dear community, I've used yocto as my workhorse in the past a lot for other processor manufacturers. Now as I'm happily joining the STM world for linux I'm stuck. Maybe it is a too easy to miss question, but which steps I have to take for putting all the needed images to the sd-card? I have followed the rules to go for using the create_sdcard_from_flashlayout.sh script with FlashLayout_sdcard_stm32mp257f-dk-optee.tsv as the parameter. After that I've used dd to flash the .raw to the designated sdcard but the board does not start at all. From the provided sdcard it starts without any issue.Where is my mistake? Regards KS

Dear all I was setting up the RISAF4 for STM32MP257, however, the partition with name "linuxkernel2" has a glitch where its size shows as givenWhich is beyond the size of my LDDR4 set to 8Gb.How to solve it? A quick reply will be appreciated.Thanking you!With regardsAmit 

I am trying to collect images from a MIPI camera that is not supported by default on the STM32MP257F-DK, but for which I have a driver. With that driver, it's seeing the camera as an attached device, and I can see it in the dmesg output and also as /dev/media2 in v4l2-ctl --list-devices. I have followed the steps at this link (modified to use the imx664 instead of imx335), and also steps I have found elsewhere (below). Is there anything I need to look for or change in order to actually see image frames from the camera, now that I can see the camera itself?media-ctl -d /dev/media2 -rmedia-ctl -d /dev/media2 -l "'48020000.csi':1 -> 'dcmipp_input':0 [1]"media-ctl -d /dev/media2 -l "'dcmipp_input':2 -> 'dcmipp_main_isp':0 [1]"media-ctl -d /dev/media2 -V "'imx664 0-0010':0 [fmt:SRGGB12_1X12/2704x1540]"media-ctl -d /dev/media2 -V "'48020000.csi':1 [fmt:SRGGB12_1X12/2704x1540]"media-ctl -d /dev/media2 -V "'dcmipp_input':2 [fmt:SRGGB12_1X12/2704x1540]"media-ctl -d /dev/media2 -

Hi!I having some issues with Linux at startup. It seems that it disabling the Bucks/LDOs at startup.vddio2: disabling vddio3: disabling vddio4: disabling vddcore: disabling v1v8: disabling v3v3: disablingWhy does this occur?Here is the complete output as attached file. As you can see, I have set up my own outputs for error handling. The device three can be found here:https://github.com/DanielMartensson/Watermelon-Wine-1A/tree/linux-testing/watermelon-wine-os%2Fcubemx%2FCA35%2FDeviceTree%2FfirmwareGood to know:clk_get_index = 143 is USART6.I have activated the RNG for TF-A only. It seems not to wake up. It's the same default configuration as DK. 

The STM32MP135 is powered by PMIC1A. After initial power-up, the voltage at BUCK4 is normal at 3.3V, but during U-Boot flashing, the output voltage at VOUT4 drops to only 2.4V, causing the flashing to fail. The VDD and VDDQ pins of the eMMC are powered by the same power rail, VOUT4.

Hi, I tried exporting the IBIS model from ST website. On importing model to SI tool I can see that there is no model assigned to DSI lines. It is showing NC. Can you share the IBIS model with MIPI drivers in it. or share some IBIS model which I can use for my simulation of MIPI line interface  

 Hi everyone,I am working on an STM32MP2 platform and facing a persistent issue with LPUART1 in interrupt mode.SetupMCU: STM32MP2UART used: LPUART1 (RS485 communication via MAX485)Debug UART: UART5 (polling mode, printf works fine)Using:HAL_UARTEx_ReceiveToIdle_IT() for RXHAL_UART_Transmit() for TXBaudrate: 115200ProblemWhen using interrupt mode, the system gets stuck in: HAL_UART_IRQHandler()The interrupt keeps triggering continuously and the system appears stuck (infinite IRQ loop).ObservationsPolling mode (HAL_UART_Receive) works perfectlySensor communication works fine in pollingIssue only happens in interrupt modeWhat I already checked NVIC enabled correctly:HAL_NVIC_SetPriority(LPUART1_IRQn, 5, 0);HAL_NVIC_EnableIRQ(LPUART1_IRQn); IRQ handler is correct:void LPUART1_IRQHandler(void){HAL_UART_IRQHandler(&hlpuart1);}No wrong handle (huart1) is used anywhereFIFO configuration added:HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8);HAL_UA

Hello, I am trying to load a kernel driver (.ko file) for a MIPI camera I would like to use with the STM32MP257F-DK. It's for the imx664, and no driver is present already. I have the source for the driver, and was able to compile it into a .ko file, cross-compiled with the exact same OS as is present on the board and with the SDK set up as required. The vermagic line matches exactly: vermagic: 6.6.78 SMP preempt mod_unload aarch64However, every time I try and load the driver with insmod, with or without -f, I get the error: insmod: ERROR: could not insert module imx664.ko: Invalid module formatI am struggling to find where the incompatibility could be, since I have re-tried it a few times and been careful to set it up as ST's documentation says and also to match what is expected by the board. Is there something I am missing with this?

Hello,I don't have so much experience with the boards of STM32 and I'm struggling a bit (actually a lot) with a quite simple task.I want to run a blinking test with the board STM32MP257F-EV1.I installed the STM32CubeMX, STM32CubeIDE and STM32CubeProgrammer.First I generated the code with CubeMX and added the code for blinking in the CubeIDE. Then I clicked on Run -> Debug and there was this error:Error message from debugger back end:Remote communication error. Target disconnected: (undocumented errno 10061).I changed the BOOT switches to 0 1 0 0, and then did Run -> Debug again. This time there was this error:Open On-Chip Debugger 0.12.0+dev-00608-gd8ed48fef (2025-02-06-11:17) [https://github.com/STMicroelectronics/OpenOCD]Licensed under GNU GPL v2For bug reports, readhttp://openocd.org/doc/doxygen/bugs.htmlsrst_only srst_pulls_trst srst_gates_jtag srst_open_drain connect_deassert_srstInfo : Listening on port 6666 for tcl connectionsInfo : Listening on port 4444 for telnet connec

I have an issue were the Linux kernel is booting, then it just stops printing out messages from USART6.Meanwhile, optee, u-boot and TF-a is printing out messages from USART6. But not Linux after a while.What can have caused this?My processor is: STM32MP257F.

Hi,I'm working on to get the multiple SAI to Codec to work synchronized as the connection below,1x MCLK1x BCLK1x FSYNC4x DIN4x DOUTWhere the three Clocks 1x lines (MCLK, BCLK & LRCLK) from one SAI master (actual pinout clock) & other SAI (pinout DIN & DOUT) sync clock internally (not sure possible b/w the SAI).SAI1 (clock master) -> MCLK, BCLK, FSYNC, DIN/DOUT -> codec1SAI2 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec2SAI3 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec3SAI4 (clock slave) -> (SAI1 MCLK, BCLK, FSYNC), DIN/DOUT -> codec4According to the TRM RM0436 Rev 7 55.4.4 External synchronization should be used between the SAI.does this need external pin connection between two SAI (all three clocks)? I'm facing error when arecord on SAI1 in the background and trying to start playback on SAI2, attached dts overlay filearecord -D hw:0,0 -f S16_LE -r 48000 -c 2 -d 0 /dev/null &sleep 1aplay -D hw:0,2 -f

Dear ST Team,I Need the clarification can I use YT9218MB in place of RTL8211F-CG ,Please recommend me , If we can then we need to use OpenWRT

Hi everyone,I'm currently validating a custom board featuring the STM32MP257 interfacing a single 16-bit DDR4 at 2133MT/s (Point-to-Point topology). I am using the ST-provided Excel tool ("Examples of DDR memory routing on STM32MP2 MPUs") to extract the Die-to-Ball Package Trace Lengths (mm).I’ve run into a few specific SI conflicts regarding the hardware guidelines, primarily driven by my PCB stackup. Due to routing density, my Address/Command (A/C) signals are split across two different layers:L6 (Bottom Layer): Microstrip. Outer solder mask is 0.6mil (Dk 4.85) over a 3.91mil 3313 Prepreg (Dk 4.4). Effective Dk is much lower due to air exposure.L3 (Inner Layer): Stripline. Sandwiched between a Core (Dk 4.6) and Prepreg (Dk 4.5). Effective Dk is approx 4.5.This leads to the following questions:1. Balancing Physical Length (mm) vs. Electrical Delay (ps): The ST guideline dictates an A/C to CLK_P/N equalization of +/- 140 mils (3.55 mm). However, if I strictly match the physical length

I am trying to build a custom Yocto Scarthgap image for a custom STM32MP153CAA3 board.I have followed the guide at https://wiki.st.com/stm32mpu/index.php/How_to_create_your_own_machine but have several issues.I have created a configuration in CubeMX 6.15.0 and exported the DTB into my project.When I try and build I get an error in u-boot ERROR (phandle_references): /soc/rcc@50000000: Reference to non-existent node or label "clk_hse"(along with references to other clock nodes)I do a `devtool  modify u-boot-stm32mp`  to get at the source code and follow through the DTB The includes from the u-boot DTB file from CubeMX are:#include "stm32mp153.dtsi" #include "stm32mp15xa.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include "stm32mp15-m4-srm.dtsi" #include "stm32mp15-scmi.dtsi"stm32mp153.dtsi includes stm32mp151.dtsi which references the clocks, which is great.However the last include, stm32mp15-scmi.dtsi then goes and deletes them all!/delete-node/ &clk_h

Hello,coming from OpenSTLinux 4.2 (mickledore) we are in the process of migrating to OpenSTLinux 6.2 (scarthgap).The process of how multiple partitions (bootfs, vendorfs, userfs) are "split out" of the rootfs appears to have changed considerably.After switching all relevant meta layers to the commit/version used in OpenSTLinux 6.2, we effectively get bitbake QA errors for every image recipe (even the ones not being built). The errors appear related to the new bbclass "stsplitpartitions".The release notes of OpenSTLinux 6.2 mention the change as "Add image class to split rootfs image on several partitions: ST SPLIT PARTITIONS", but fail to provide any guideline on how to migrate existing projects to the new partitioning scheme.For testing, I removed all our proprietary layers and only kept the ST layers and standard Bitbake/OpenEmbedded layers.But the errors persist even for this minimal setup when building the standard ST image recipe st-image-core.How does st-split-part

Hi,I recently just finished the Yocto Bringup of a custom STM32MP15FAA1. Everything seems to be working in my application. I am now looking to begin development of the M4 in which I need access to either SWD or JTAG to do lower-level development. Unfortunately, I am having trouble connecting to either interfaces through both CubeIDE and also manually inputting OpenOCD in an IDF Powershell instance.I presume the easiest way to get to my goal is to setup SWD which on the MP15 maps to TMS (SWDIO) and TCLK (SWCLK) and I connected GND and VCC. My STLinkV3-MIME detects 3.3V on the reference line but can never connect to target. This is my first time working with a SOM as most of my development is on base Cortex M microcontrollers so I have a few questions.1. Is there anything in the M4 device tree that can be preventing JTAG from operating like the STPMIC? I do have M4 RPROC enabled in my device tree and the file descriptor is available for me to access.2. Does the boot mode matter? My end a

Hi,We are building Linux for STM32MP157D using Buildroot, and we are experiencing an issue where the boot process sometimes does not proceed from BL2 to OP-TEE, and sometimes OP-TEE does not proceed to U-Boot.Occasionally, the kernel does boot successfully.Could this be caused by incorrect DDR3 controller settings? We are using a custom board.If so, would compiling the STM32DDRFW-UTIL source code and using it in engineering mode be the right solution?I have read that for some chips it is possible to perform automatic tuning and receive the optimal configuration as a result.Is this possible in this case? If not, what is the proper method to determine the correct DDR controller settings?If DDR is not the issue, do you have any other suggestions?For testing with DDR-UTIL, I see that there is no development board listed for the 157D series, as the utility supports "STM32MP157C-EV1_DDR_UTILITIES_A7".If we order the "STM32MP157D-EV1", will I be able to run DDR tests on it to compare with our

Hi everybody,For a project, we need to start the STM32MP257F in the M33 flavor, in order to perform some basic functions (GPIO, I2C, UART) in the lowest power mode possible (DDR unpowered, A35 in low power mode — i.e., no remoteproc nor Linux). The goal is to compare MP257 capabilities compared to IMX8 (goal line end of this month)I use Yocto/bitbake to compile for our custom board.Following the StarterApp_M33TD_CM33 example, I've encountered the following difficulties:1) How can I debug the BL2 part?From the post STM32MP257 programming via JTAG - STMicroelectronics Community , I see that JTAG can be used to debug the STM32MP257 using CubeIDE.2) How can this be done?I tried to modify the *.ld file used by StarterApp_M33TD_CM33 to place the code in internal RAM instead of DDR, but it doesn't work. On the UART console I see BL2 logs, but nothing from this app, and since I can't debug, I don't know what's happening.3) How do I modify the project/Device Tree or other elements to execu

I was handed an existing build that creates an SD card image for STM32MP1 and, while the partition allocated for the root filesystem is a gargantuan 9G, it's clear the filesystem created inside it is much smaller -- around 512M -- and I'm already at 98% full. I'm using ST's SD card image creation script, and I have looked for the variable where I can specify a larger root filesystem. I've seen a couple other posts here that provide suggested solutions, but those don't appear to work. Is there a single controlling variable that identifies the desired size of the actual root filesystem (independent of the size of the containing partition)? I'm assuming that value would be fed to a "mke2fs" command somewhere. P.S. I'm using the walnascar release of the meta-st-stm32mp layer.

Hi,I have few custom boards with STM32MP257 mostly running PTP related tasks. Once in a while (once in a few days of continuous run) I have noticed the following error in the dmesg (as it seems UART related - I have 4 UARTs enabled in the DT, while 3 of them have DMA enabled (the console one does not have the DMA enabled), but only one UART (other than console) is being used in the system for RX only):[251158.390476] Unable to handle kernel paging request at virtual address dead000000000108[251158.392934] Mem abort info:[251158.395854] ESR = 0x0000000096000044[251158.399679] EC = 0x25: DABT (current EL), IL = 32 bits[251158.405114] SET = 0, FnV = 0[251158.408235] EA = 0, S1PTW = 0[251158.411457] FSC = 0x04: level 0 translation fault[251158.416489] Data abort info:[251158.419408] ISV = 0, ISS = 0x00000044, ISS2 = 0x00000000[251158.425041] CM = 0, WnR = 1, TnD = 0, TagAccess = 0[251158.430173] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0[251158.435607] [dead000000000108] address between us

Hello,I am currently working with the STM32MP157-DK2 platform and would like to integrate OpenPLC into my Yocto-based Linux distribution.I would like to inquire whether STMicroelectronics provides any existing Yocto layer or recipe for OpenPLC. If no official support is available, I would appreciate guidance on the recommended approach to create a custom Yocto recipe for integrating OpenPLC into the build system.Specifically, I am looking for best practices regarding:Creating a custom layer for OpenPLCWriting a BitBake recipe for OpenPLC (including dependencies and build steps)Integrating OpenPLC runtime with the STM32MP1 ecosystemAny potential compatibility considerations with the STM32MP157-DK2Any references, documentation, or examples would be highly helpful.

Hi,I'm designing a board with STM32MP153FAD and have a question about DDR layout reference.Which reference should I follow for the DRAM section?Eval kit MB1272C_03 layoutST's published reference DDR layout.Questions:Which is the recommended reference for custom board design?Is there a design guide specifically for STM32MP153 DDR layout and routing guidelines?Is there a document listing pin delays for the FAD series SoCs? This would be helpful for length matching calculations.Best regards,Batuhan

Hi, I am working on STM32MP257F-EV1 Evaluation Board. I want to use shared memory (like DDR) between M33 and A35 cores. M33 should write data samples collected form peripherals in shared memory array and A35 should read this memory array to process it further. How to achieve this?