STM32MP257F-EV1: M33 cannot initialize SPI3 after assigning RIF ownership to CID2 (HAL_SPI_Init hangs/faults)

[Amruta_Dixit]

Hi,

I am trying to use SPI3 from the Cortex-M33 on the STM32MP257F-EV1 running OpenSTLinux 6.6 (Scarthgap).

Software versions

• Board: STM32MP257F-EV1
• OpenSTLinux: 5.0.15
• Kernel: 6.6.116
• STM32Cube_FW_MP2_V1.3.0
• M33 application based on OpenAMP_TTY_echo_CM33

What I changed

I modified the OP-TEE RIF configuration file:

external-dt-v6.0-stm32mp-r3/stm32mp2/a35-td/optee/stm32mp257f-ev1-ca35tdcid-ostl-rif.dtsi

I changed SPI3 ownership from CID1 to CID2:

RIFPROT(STM32MP25_RIFSC_SPI3_ID,
        RIF_UNUSED,
        RIF_UNLOCK,
        RIF_NSEC,
        RIF_PRIV,
        RIF_CID2,
        RIF_SEM_DIS,
        RIF_CFEN)

I also assigned the SPI3 GPIO pins to CID2:

• PB7
• PB8
• PB10

using:

RIFPROT(... RIF_CID2 ...)

Then I rebuilt:

• OP-TEE
• FIP

and flashed the new images while keeping the original TF-A.

Verification

Using a small RIF access test on the M33, I verified that SPI3 is now accessible.

Before:

RIF CRC=0 I2C1=0 UART5=0 SPI3=3

After modifying the RIF configuration:

RIF CRC=0 I2C1=0 UART5=0 SPI3=0

So the peripheral ownership appears to be correct.

M33 code

The M33 application enables the SPI3 clock and initializes SPI3 using HAL:

__HAL_RCC_SPI3_CLK_ENABLE();

HAL_SPI_Init(&hspi3);

GPIO is configured as:

PB7  MOSI
PB8  MISO
PB10 SCK
AF2

SPI configuration:

SPI_MODE_MASTER
SPI_DIRECTION_2LINES
SPI_DATASIZE_8BIT
SPI_POLARITY_HIGH
SPI_PHASE_2EDGE
SPI_NSS_SOFT

Problem

The application never reaches successful SPI operation.

It appears to stop during or immediately after:

__HAL_RCC_SPI3_CLK_ENABLE();

HAL_SPI_Init(&hspi3);

The clock enable macro expands to:

SET_BIT(RCC->SPI3CFGR, RCC_SPI3CFGR_SPI3EN);

which makes me suspect that the M33 may still not have permission to access the corresponding RCC resource.

Questions

1. Besides assigning STM32MP25_RIFSC_SPI3_ID to RIF_CID2, are there additional RIF entries required for SPI3?
2. Does the M33 also need ownership of the RCC resource controlling SPI3CFGR?
3. If so, which RIF_RCC_RESOURCE(x) corresponds to SPI3CFGR / SPI3_R?
4. Are there any additional security, clock, reset, or firewall settings required for SPI3 on STM32MP257 when accessed from the M33?

Any guidance or working example of SPI3 running from the M33 on STM32MP257 would be greatly appreciated.

Thank you.