STM32 MCUs Security

Hi,I am trying to use the STM32Cryptography library to verify the signature of a flash segment, using RSA Encryption and 3072 bit length keys.The signature is generated by a python script and appended to the hex file. The signature has a length of 384 bytes, just like the modulus that is fed to the script and the STM application.When calling the verify function (cmox_rsa_pkcs1v22_verify) the return value indicates the modulus is too short (retval = 0x50007). How can the library determine that the modulus is too short when the input variables show a length of 384 bytes for the signature and the modulus? I was under the impression that the signature was just an integer, is there some format that the signature has to adhere to?In the following excerpt you can see the code, that I use to reproduce the error. The first verification against the computed value is successful as it should be. However the second verification against the python_signature returns 0x50007. Although the passed sizeo

I could not get wanted result by using STM32F7 calculation unit. The code I borrowed for comparison was from WireShark CRC32 function. It was a table based function for speed. And I compared the STM32 CRC result with bitwise algorithm. I found out that STM32 CRC unit by default gives the same result as the named one CRC32Mpeg2.But I failed to set STM32F7 CRC unit to give the same result of WireShark CRC32 after I tried all reasonable combinations of parameters.I've read quite a lot online articles and there could be mistakes involved with CRC calculation. The most notorious issue comes from the shifting direction. And the table and the shifting direction mismatch, input data reflection(or inversion from STM32 datasheet), initial CRC value and so on.And I think there are ambiguities about byte inversion and output data inversion. We can think of more than 1 operation with input data inversion and output data inversion. Especially I wonder when the output inversion is applied, every byte

I can "Transmit" but the TXE flag never clears and the transmit times out. It's unclear which parts of the bus are fully automated (reset, discovery, etc.) and how much of the CRC is handled, etc. I can see nothing on a scope, but if the chip gets in an odd state and never tries to send that would match what I'm seeing. Without better register descriptions or some example that can talk to a 1wire EPROM I'm kinda stuck.

We have a design based on STM32H735RGV6. We are trying to move our design to STM32H725RGV6.These two MCUs are pin compatible and can be used in the same design without changing the board design.However, we are not sure about using the same software in these two MCUs.Is there any limitation to using the same software for these two MCUs.Note that: We are not using crypto/hash feature of STM32H735RGV6.

Hi,There is No-Stretch Get Memory Checksum command in I2C bootloader, Does someone know the CRC algorithm used?The UART & SPI bootloader, Host can set the CRC polynomial & CRC initial value in Get Checksum command, but there is no such description in this command of I2C bootloader.Thanks a lot,Best RegardsFrank

We are facing an issue related to the STM32H753 MCU , CubeIDE version 1.10.1 .We compiled our project successfully with all needed scripts for generate the SBSFU file + sfb bin file.The bin file programmed into the internal FLASH via the Cube Programmer, but the FW is not running.If we are compiling the project with debug configuration ( meaning without packing it to SBSFU bin file ) ,the FW is running without any issue.I saw in ST forum that there is a known issue from 3.2022 which is related to the SBSFU file.Issue building SBSFU with latest STM32CubeIDE 1.9.0 : here is the solutionWe will be happy if you have any idea what we are missing here .

Hi,I'm playing with Nucleo-u575zi and GPIO_IOToggle_TrustZone example.Everything is working as expected.I want to be sure that systick of secure zone is never blocked by nonsecure zone (e.g. setting PRIMASK_NS =1). In secure mode, at startup, I then set AIRCR.PRIS=1 (SYSTICK_S priority is set to '1').I would expect that setting PRIMASK_NS to one boosts the current execution priority to 0x80, but it's also masking SYSTICK_S irq (it stops to be triggered, so non secure world is "killing" secure world).Am I missing something?

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Device: STM32L4S5Trying to run x-cube-aws v2.2.1I've successfully flashed the B-L4S5I-IOT01_STSAFE_Provisioning binary (output below)Start provisioning of STSAFE-A   Force STSAFE-A provisioning   Launching STSAFE-A pairing Check if Pairing Host keys available Pairing OK   Erase Data : OK   Now Store Certificate STM_POC_SBSFU_ROOT_TEST_CA_00 inside STSAFE-A Certificate STM_POC_SBSFU_ROOT_TEST_CA_00 successfully written inside STSAFE-A : OK   Now Store Certificate STM_POC_SBSFU_OEM_TEST_CA_00 inside STSAFE-A Certificate STM_POC_SBSFU_OEM_TEST_CA_00 successfully written inside STSAFE-A : OK   Now reading and compare Certificates written inside STSAFE-A :   Get Certificate CERT_CA_FW OK Certificate CERT_CA_FW successfuly read and compared : OK Get Certificate CERT_CA_OEM_FW OK Certificate CERT_CA_OEM_FW successfuly read and compared : OK   End provisioning of STSAFE-A The next step, which was to flash SBSFU results in the following= [SBOOT]

Hello STM32U5 community,I was making a few attemps with my B-U585I-IOT02A demo board and TF-M. I am afraid I have irreversibly locked the MCU.Here is what I did:run regression.shset RDP level 1 with the Programmer despite the warnings, because I forgot that regression.sh had erased the Secure and NSecure applications.Now I fail to reconnect with the MCU by any means. What can I do? TZEN/RDP regression with boot from RSS? AN5347 says "a small rework" must be done. I would appreciate a step by step instruction.Regards.

On switching from secure to non-secure mode using a function pointer (with the cmse_nonsecure_call attribute) in STM32L562(ARM Cortex M33), general purpose registers R0-R4, R12 and floating point registers S0-S15 are not restored when back in secure mode. There is an explanation for R0-R3, R12 and S0-S15 as they are scratch registers. But R4 should recover its value once back in secure mode, but is getting corrupted. Does anyone have an explanation for this please?Below is the assembler code for the switch from secure to non secure mode. The IDE used in STM32CubeIDE v1.8.0 and compiler used is gcc-arm-none-eabi-10-2020-q4-major-win32.

Hi ST Team,I'm working on a project where I'm using SBSFU as bootloader (on a STM32H7). When I download the new firmware image, SBSFU reboot the system and start execution (decrypting image, validating and so on...). While SBSFU is doing these actions I would like to update a simple display that is made by 7-segment LEDs, so I need to manage it inside an interrupt routine. I notice that when the code jumps inside SECore code it disables the interrupt for a long time causes flickering on the display.How can I manage that situation?Thanks a lot in advance?GDV

Hi,I am working on enabling hardware cryptography in nucleo-u585ai board.Can you suggest an example for enabling hardware cryptography? or Is it enabled always?How to test or know that data is encrypted?Thanks,Akanksha

Hello,A hard fault exception is being thrown when I flash the SBSFU_userapp.bin file with the STM32Cube Programmer to device that uses the WB55 MCU architecture (M4/M0+) and then try to run the SBSFU example in Tera Term. The secure engine is first initialized and then hits the hard fault error after "CHECK USER FW STATUS" then loops again to the secure engine initialization and continues this process until I disconnect from the device from Tera Term. I have provided a screenshot to illustrate the issue. I don't have any idea on how to debug this and would appreciate any feedback on this issue and how I can go about resolving it. Hardware:Device with M4 (user application execution)/ M0+ (network stack)ST-LinkV3Mini board attached to a micro-b to usb cableribbon cable that connects from header pins on ST-LinkV3Mini to another header on device to be programmedSoftware:STM32Cube ProgrammerTera Term

Hi,Where can I find how the protection against DPA attacks implemented in the STM32U585 microcontroller works?I couldn't find anything in the datasheet and reference manual.Thanks

In my application, I have a sequence which looks something like this:Load an AES key from CKS using SHCI_C2_FUS_LoadUsrKeyCall HAL_Cryp_Init, HAL_Cryp_Decrypt, and HAL_Cryp_DeInit to decrypt a block of dataUnload the key from CKS using SHCI_C2_FUS_UnloadUsrKeyLoad an AES key from software (not CKS)Call HAL_Cryp_Init, HAL_Cryp_Decrypt, and HAL_Cryp_DeInit to decrypt another block of dataThis sequence can be repeated several times.I ran into an issue which presented itself as follows:On the first pass through that sequence, everything worked greatOn subsequent passes, the decryption using CKS produced the wrong resultI think I've tracked this down to a problem with the AES_KEYR0..7 registers. On the first pass through, when I call the decrypt function after loading the key from CKS, the AES_KEYR0..7 registers are all zero. On subsequent passes, the AES_KEYR0..7 registers contain the value left over from step 5. This seems to interfere with the use of the CKS key.If I add the following co

In some ST documents the STM32L0X1 is listed as having an RNG peripheral and older versions of the CMSIS headers list the RNG register addresses. Moreover, enabling the peripheral and using it appears to generate random numbers. However newer manuals and CMSIS headers appear to have removed references to the RNG. What's the situation?

Hi,I'm using some STM32 drivers code to parse X509 certificates. These drivers are based on ECC cryptography. I need to change to RSA. I need utilities such as parseCert()isValidCert()isParent()which exist for ECC, but I cannot find any equivalents for RSA cryptography.Specifically, I need to check a chain of trust of RSA certificates, and I also need to call RSA_PKCS1v15_Verify() for an RSA signature, so I need to pass in the public key in a structure RSApubKey_stt, and this has to be extracted from the leaf certificate.The target MCU is STM32H753.The ECC-based X509 utilties I'm working with are dated 24-february-2017.Do such utilities exist for RSA? Or do I have to write them myself?Thanks

Looking for the MCU specs with the following key requirements:              - 24 IO : 8 input, 8 outpt, 8 x LEDs              - secure boot features              - hardware reset - backline support – CAN Bus communication at 5VCan STM32G4 support above mentioned features?

I use my own application to program different devices, arm in particular. Now, i'd like to support stm32L552. So, if TZEN = 0 it works fine. if TZEN = 1, DBANK = 1, SECWM1_PSTRT - set as secure, SECWM2_PSTRT - set as non-secure, RDP = 0xaa (level 0) i cant read flash using SWD. STM32CubeProgrammer works perfectly in both cases.I'd appreciate any help

In my project the microcontroller is STM32F756VGT6, I changed the example "2_Images_OSC" of STM32f769I-Discovery to be compatible with this microcontroller.Right now everything seems O.K and I can upgrade the application with SBSFU. But when I uncomment the definition of SFU_MPU_PROTECT_ENABLE I get to a problem and here is the message I get from terminal:====================================================================== = (C) COPYRIGHT 2017 STMicroelectronics = = = = Secure Boot and Secure Firmware Update = ======================================================================     = [SBOOT] SECURE ENGINE INITIALIZATION SUCCESSFUL = [SBOOT] STATE: CHECK STATUS ON RESET INFO: A Reboot has been triggered by a Software reset! Memory fault ========= End of Execution ==========Here is the MPU config:#define SFU_PROTECT_MPU_MAX_NB_SUBREG (8U)   /** * @brief Region 0 - Enable the read/write operations for the full peripheral area in unprivileged * mode. * Executio

We are having issues with corrupted flash on the STM32 H7 series. The problem manifests where a read to the offending address in flash will cause a bus fault. We think it is down to bad CRC and the way to resolve is usually to wipe the flash and reprogram. What I would like to do is do this on the fly, so detect the offending address and erase the page. I was hoping to do this roughly though the following:// enable the busfault handler SCB->SHCSR|= SCB_SHCSR_BUSFAULTENA_Msk;   // disable all faults __disable_fault_irq(); __DSB();   // read the offending data here read()   // check the outcome if (SCB->SHCSR & SCB_SHCSR_BUSFAULTPENDED_Msk) { // erase the sector here }   // reset __enable_fault_irq(); __DSB(); SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTENA_Msk;However this does not work - the fault is prevented correctly but the pending bit is never set and I don't seem to have anyway to detect that a bus fault would have occurredWhat am I missing? Or am I

Hi,I tried to execute my custom SBSFU_UserApp.bin on the STM32H7B3I-DK board and I get error for Header signature verification failure in slot SLOT_ACTIVE_1. I have made changes in se_crypto_bootloader.c file for adding RSA signing verification in place of ECDSA. I want to debug the changes inside of se_crypto_bootloader.c file of SECoreBin project.I am using STM32Cube IDE and compiling the applications as per the order mention in the readme file of the STM32H7B3I-DK 1_Image demo project.Please let me know, what is the debug mechanism for SECoreBin application? How can I enable debug mode of SBSFU Secure Engine application?Thanks,Ikbal

I'm currently trying to use the CRC peripheral on an STM32G474, and when running HAL_CRC_Calculate(), the computed checksum is always zero. Doing some debugging into the HAL_CRC_Init() function, I've found that when the WRITE_REG macro is called, nothing happens.Here's an example:Before calling WRITE_REG, hcrc->Instance->POL = 0.After executing this line, the value should be 79764919, but: hcrc->Instance->POL is clearly still 0.

I'm creating a new lora project starting from STM32Cube_FW_WL_V1.2.0, application LoRaWAN_SBSFU_1_Slot_DualCore.I reserved some space (from 0x0801A000 to 0x0801BFFF) for some configurations. I modified the file mapping_fwimg.ld like below.\STM32Cube_FW_WL_V1.2.0\Projects\NUCLEO-WL55JC\Applications\LoRaWAN_SBSFU_1_Slot_DualCore\Linker_Common\STM32CubeIDE\mapping_fwimg.ld/* Dwl slot #1 : (2 kbytes) */SLOT_Blob_Dwl_1_start = 0x08002800;SLOT_Blob_Dwl_1_end  = 0x08002FFF;/* Active slot #2 (92 kbytes) */SLOT_Active_2_header = 0x0803F000;SLOT_Active_2_start  = 0x08003000;SLOT_Active_2_end   = 0x08018FFF;/***** NVM FLASH Data *****//* WARNING: Symbols not used. The NVMS address is defined in lora_app.c */LW_NVM_ROM_start__  = 0x0801A000;LW_NWM_ROM_end__   = 0x0801BFFF;/* Active slot #1 (60 kbytes) */SLOT_Active_1_header = 0x0803F800;SLOT_Active_1_start  = 0x0801C000;SLOT_Active_1_end   = 0x0802A