FAQ: STM32MP1 how to configure Ethernet PHY Clocks

During Ethernet bring-up in Linux, the following error appears: "stm32-dwmac 5800a000.ethernet: Failed to reset the DMA."

What does this error mean? How are the STM32MP1 Ethernet clocks for the Ethernet PHY configured in Linux and in U-Boot? How is the clock configuration checked?

Explanation  

The issue occurs because the PHY does not provide the clock to the GMAC. As a result, the GMAC cannot reset at Ethernet startup.

The required clocks depend on the GMAC interface: MII, GMII, RGMII, or RMII.

Application note AN5031, Section 10.1.13, provides Ethernet application examples with the different possible hardware designs:

1. RMII with 25 MHz crystal on the PHY; REF_CLK from the PHY (AN5031 Rev 3, Figure 44)
2. RMII with 25 MHz on the ETH_CLK pad from the internal RCC, without a PHY crystal; REF_CLK from the PHY (AN5031 Rev 3, Figure 44)
3. RMII with 50 MHz on the ETH_CLK pad, without a PHY crystal; internal REF_CLK from the RCC (AN5031 Rev 3, Figure 45)
4. RGMII with crystal on the PHY; ETH_CLK125 from the PHY (AN5031 Rev 3, Figure 46)
5. RGMII with 25 MHz on ETH_CLK, without a PHY crystal; ETH_CLK125 from the PHY (AN5031 Rev 3, Figure 46)
6. RGMII with 25 MHz crystal on the PHY; internal CLK125 from the RCC (AN5031 Rev 3, Figure 49)

For each clock configuration in a design, find the corresponding Linux and U-Boot device tree configurations at https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#DT_configuration.

This wiki article provides practical information

RCC Ethernet Clocks 
 

You can see the GMAC clock configuration for the PHY in the RCC reference manual 0436rv5 fig 83 
§ RCC  Peripheral clock distribution for Ethernet
3 main STM32MP1 pads are to be considered between STM32MP1 GMAC and PHY: 

• The ETH_CLK pad which provide a clock to the PHY.
• The ETH_REF_CLK pad or ETH_CLK125 pad to get reference clock from the PHY.

Depending on the configuration of your design, you have to configure the device tree, the ethernet driver controls the clock configuration via the below registers. 
ETH_CLK_SEL, ETH_REF_CLK_SEL and ETH_SEL are controlled via the register SYSCFG_PMCSETR.
ETHMACEN,ETHRXEN,ETHTXEN,ETHCKEN are controlled by RCC_MP_AHB6ENSETR.
ETHSRC is controlled by RCC_ETHCKSELR.

Device tree properties
 

Linux device tree properties are defined in linux/Documentation/devicetree/bindings/net/stm32-dwmac.txt in the STMicroelectronics/linux master branch.

"eth-ck": When no crystal feeds the PHY, the microprocessor unit (MPU) on pad ETH_CLK provides the 25 MHz or 50 MHz clock to the PHY. In this case, the clock (from ETH_CLK feedback) is provided by PLL4P or PLL3Q. This configuration corresponds to examples 3 and 6 in AN5031.

1. Add the clock to the device tree (DT) Ethernet node:

clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "ethstp", "syscfg-clk", "eth-ck";

clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, <&rcc ETHSTP>, <&rcc SYSCFG>, <&rcc ETHCK_K>;

<&rcc ETHCK_K> enables eth_clk_fb; see Ethernet figure 83, top-right corner.

2. Ensure that the TF-A device tree st,pkcs property contains CLK_ETH_PLL4P or CLK_ETH_PLL3Q and that the enabled ck_kern_eth clock is present. This change updates the RCC_ETHCKSELR.ETHSRC bit.

3. Ensure the used PLL setting define a 25 MHz or 50 MHz.
    

• Set the st,eth-clk-sel Boolean property in the RGMII PHY when the PHY does not provide a 125 MHz clock to the ETH_CLK125 pad

The ETH_CLK125 pad is not used. The RCC provides a 125 MHz clock to the GMAC.

• In RMII mode, set "st,eth-ref-clk_sel" in the kernel and "st,eth_ref_clk_sel" in U-Boot when the PHY does not provide ETH_REF_CLK.

The ETH_RX/REF_CLK pad is not used. The reference clock for RMII comes from the reset and clock controller (RCC) (eth_clk_fb).

Do not set this property in RMII when the STM32MP1 reference clock comes from the external PHY through the ETH_REF_CLK pad.

How to check the clock configuration

Dump the state of SYSCFG_PMCSETR

1. Enable SYSCFG clk
devmem2 0x50000A10 w 0x10800

2. Read SYSCFG_PMCSETR                                                                                                                    
devmem2 0x50020004
Dump the state of RCC_MP_AHB6ENSETR
devmem2 0x0x5000021C
in uboot md.l  0x5000021C 1
Dump the state of RCC_ETHCKSELR
devmem2 0x0x500008FC
 

Additional resources

For other issues at bring-up, refer to STM32MPUs bring-up troubleshooting guide