The signal integrity is mostly ensured if the design follows the recommended length constraints and other rules in explained in the below routing guidelines.
For a successful design, ST recommends reusing, as much as possible, the Altium PCB layout projects provided in the ST evaluation boards. Alternatively, the Altium projects in the STM32MPx series DDR memory routing guidelines example .zip files.
To find the Altium projects, click the following link:
In these .zip files, there are different DDR topologies and DDR types. Furthermore, different MPU packages are available (notice that the signal and power integrity tests have been done). Many customers follow this template and DDR in signal integrity issues are very seldom.
For length equalization of the DDR signals, ST provides in the SMT32MP1/2 series DDR routing guideline examples zip, an excel sheet with STM32MPx SoC internal lengths of the DDR signals. It helps to compute the total length of the tracks.
For signal integrity simulation the STM32MP1x IBIS model files are also available in the ST web site of the STM32MPUx page, go to CAD resources and check IBIS model.
AN4803 presents the usage of these IBIS model files.
Regarding the STM32MPx DDR controller timings follows the JEDEC standard. The timings are very standard timing across the brands. The timing depends on the DDR type, DDR datasheet, clock frequency, the DDR topology (density), and the DDR speed Grade/bin. The DDR controller strictly applies these timings that are described in JEDEC, they are not in the STM32MP1x datasheet.
STM32CubeMX generates the FSBL device tree file for these timings. Some preset device tree files for typical DRAM @ typical frequencies are available in the OpenSTLinux sources files. Notice that the DDR PHY timings (different from DDR timings) are computed by internal PHY firmware at boot.
The application note "DDR configuration on STM32MPx series MPUs" provides the configuration of the impedance matching insights on the DDR controller itself.
