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When sliding the screen in TouchGFX, some widgets may experience rendering issues causing flickering. What could be the root cause, and are there any solutions?The images are all in the external QSPI Flash. Could this be the reason?

I'm working with an STM32F411 and trying to run two I2S master-receiver interfaces (I2S1 and I2S2) at the same time, each receiving data from a pair of PDM microphones using DMA circular transfers.However, I found a very strange and extremely hard-to-debug issue:Observed abnormal behaviorWhen only one DMA is enabled, both I2S1 and I2S2 work correctly.When both I2S + DMA are enabled at the same time, the following happens:If I2S1 has no microphone connected, it correctly receives all zeros.If I2S2 does have a microphone connected, then I2S1 suddenly starts receiving non-zero data, even though no microphone is connected to I2S1.It looks like I2S1 is receiving data that actually belongs to I2S2’s DMA buffer.Sometimes the behavior changes depending on the order of calling HAL_I2S_Receive_DMA().Both DMA buffers are allocated as global arrays (4 × 512-word buffers).I also tried disabling JTAG on PA15 (I2S1_WS), but the issue still exists.DMA configI2S1 RX → DMA2 Stream2I2S2 RX → DMA1 Stream3

Hello everyone, I’m new to STM32 and I’m currently stuck with using timers.I’m working with an STM32F303RE, and the goal of my project is to generate 6 signals at 100 kHz (high time between 100 and 500 ns), each phase-shifted by 60°. These signals will be used to phase-shift power commands, in order to limit current spikes by staggering their switching times. For now, I’m focusing on generating just a single 100 kHz signal with a longer high time so I can easily observe it on an oscilloscope (precise timings are not important at this stage). To generate the signal, I thought about using the combined PWM mode of Timer 1. If I understand correctly, this mode allows the output to go high when the timer reaches CCR1, then go low when it reaches CCR2, and remain low until the ARR is reached or the timer restarts. This method has the advantage of potentially generating 2 (or 3?) signals using TIM1 and CCR1–6, and makes it easy to handle phase shifts. I have already tested

STM32 MCUs hide surprisingly useful hardware features that can save you CPU cycles, lower power, make multi-core life easier, and fix intermittent bugs — if you know they exist. This article reveals 5 “hidden” STM32 features (with concrete examples and code) that even experienced MCU engineers often forget, and exactly how to use them safely in production. Feature 1 — Fast-mode Plus I²C (FM+, up to 1 MHz) Fast-mode Plus (FM+) is an I²C mode that supports communication speeds up to 1 MHz, which is faster than Standard mode (100 kHz) and 2× faster than normal Fast-mode (400 kHz). Why does FM+ exist? Standard 400 kHz I²C couldn’t keep up with: High-speed sensors High-refresh displays Real-time control loops Large configuration registers in ICs Interrupt-driven or polling-heavy systems FM+ allows faster transfers without switching to SPI. Why is FM+ “special” in STM32? Most STM32 MCUs have: Dedicated FM+ pins (because they need stronger current capability) Hardware fil

Hi, I need a little explanation about what is wrong behind my reasoning..I am using STM32F411. reading, two inputs of ADC in scan mode over circular DMA triggered via TIM2 update event.TIM2 is triggering ADC at 100KHz, so I have 50Khz sample rate per adc input. At input of both ADC channels I connected signal generator feeding 1Vrms sine @20KHz.Everything works ok, I am using printf of both channels over (USB-CDC) as  and I can see two sinusoide signals on serial plotter. I am using this serial plotter:https://web-serial-plotter.atomic14.com/ Now the problem and confusion starts here:If I change only TIM2 frequency to 10KHz, I am getting 10X lower sample rate also (now 5KHz pre channel, all checked with Logic Analyzer), but I still can see clear 20KHz sine at serial plotter, without degradation and this contradicts Nyquist theorem...How is this possible and what I am missing?

Hello,I recently updated my CubeMX version from v6.14.1 to the latest, and am no longer able to open the .ioc file. Selecting "continue", results in attempting to unzip DB.6.0.141.tar.bz2 where it hangs until failing.Selecting "migrate" results in the following error, "Range [14, 2) out of bounds for length 2".My team is seeing this issue on Windows and Linux.

So i'm trying to install X-CUBE-MEMS1 in the IOC file of a STM32N6-DK board.  The problem i can't seem to install it?  All the tabs are greyed out and have little red cpu marks by them.  Is X-CUBE-MEMS1 supported on STM32N6 processors?   When i go to the github page it also doesn't like there there's drivers for to many chips inside of it?* https://github.com/STMicroelectronics/X-CUBE-MEMS1/tree/main/Drivers 

Hello! I am designing a wide input range flyback converter using the altair04-900 for my formula student team.For testing the switching behaviour, I simulated the ALTAIR04-900 using the schematics in the datasheet of figure 4-7. figure 4-6 shows results comparable with the values specified on the datasheet- with Idss(off) being 104uA instead of 80uA. Simulating figure 7 I made the following assumption: the IC should actually switch. My reasoning: Icc has the value of the operating current as stated in the datasheet. However the simulation results show discrepancies (reference see „simfigure7“); Icc has the expected value, but voltage at ZCD never goes above arming threshhold, therefore the IC should not be able to switch. My explanation: Some kind of brown-out, as Vzcd is below the internal clamping voltage as stated in the datasheet. Also notable: Vdc above 2.79V on COMP pin gives a converging error. Instead, I used a close value of 2.79Vdc. For further testing I altered figure 7 (ref

I've just received a brand new DK from Mouser and I've been trying to get the stock AI demo up and running. The camrea is connected, power is provided via a short USB-C cable on the 2nd USB connector (not the ST-Link one) and the jumpers changed over.When I launch the AI demo via the touchscreen, the camera feed appears but there appears to be noise on the display. The camera stream appears for a few seconds before the screen greys out.Video attached.

If on a STM32H747 the Cortex-M4 (BCM4 or BOOT_M4 Bit) is disabled by software, it is impossible to reactivate it with the STM32CubeProg v2.18.0 because the checkbox disappears in the user interface. But this happens only if you do a power cycle and reconnect to the target.

Hi,I've recently been trying to get an LRUN application up and running on the NUCLEO-N657X0-Q board. Similar to the posts in https://community.st.com/t5/stm32cubeprogrammer-mcus/stm32n6570-dk-unable-to-erase-external-flash/td-p/757897, I cannot access the flash for erasure, with errors indicating to verify flash memory protection. I currently have the BOOT0 jumper on 1-2 (for 0) and BOOT1 on 2-3 (for a logical 1), which should be putting me into the Development boot mode. For external loaders, I have MX25UM51245G_STM32N6570-NUCLEO selected. I've tried both full chip erase and sector erase, both giving me errors that tell me to verify flash memory protection.Please advise, I'm not sure what I'm doing wrong. This is my first time attempting to flash the memory.EDIT: I should've mentioned, I'm using STM32CubeProgrammer 2.20.0. I've tried this on both Windows 11 and Ubuntu 24.04EDIT #2: I have also attached the verbose log file after I hit "full chip erase" and a single

I aim TO drive a mipi display screen on STM32MP257F-EV1, so I have to understand the DRM framework.After flash the new firmware, I found that the modetset always shows errors, so I want to confirm whether the support in this aspect is OK? But watching your previous video, it can drive LVDS screen, so I feel very strange, is there anything else I need to pay attention to? STM32_Programmer_CLI -c port=usb1 -w ./flashlayout_st-image-weston/optee/FlashLayout_sdcard_stm32mp257f-ev1-ca35tdcid-ostl-m33-examples-optee.tsv   root@stm32mp2:~# modetest -M stm failed to open device 'stm': No such file or directory as you can see, all are failed. root@stm32mp2:~# modetest trying to open device 'i915'...failed trying to open device 'amdgpu'...failed trying to open device 'radeon'...failed trying to open device 'nouveau'...failed trying to open device 'vmwgfx'...failed trying to open device 'omapdrm'...failed trying to open device 'exynos'...failed trying to open device

The first case concerns the DAC, by setting "Output Buffer" = Disable in CubeMX, it is enabled in code generation instead, i had to add "DAC1->MCR = 0x03" in the initializations. /** * @brief DAC1 Initialization Function * @PAram None * @retval None */ static void MX_DAC1_Init(void) { /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ LL_DAC_InitTypeDef DAC_InitStruct = {0}; /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC1); /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC channel OUT1 config */ DAC_InitStruct.TriggerSource = LL_DAC_TRIG_SOFTWARE; DAC_InitStruct.WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; DAC_InitStruct.OutputConnection = LL_DAC_OUTPUT_CONNECT_INTERNAL; DAC_InitStruct.OutputMode = LL_DAC_OUTPUT_MODE_NORMAL; LL_DAC_Init(DAC1, LL_DAC_CHANNEL_1, &DAC_InitStruct); LL_DAC_DisableTrigger(DAC1, LL_DAC_CHANNEL_1); /* USER CODE BEGIN DAC1_Init 2 */ /*

Hi, I started a new project with STM32U031C6. When I enabled Independent watchdog (IWDG), STM32CubeIDE generated the following line in the MX_IWDG_Init function:     __HAL_RCC_IWDG_CLK_ENABLE();When compiling the project, an error is generated:     undefined reference to '__HAL_RCC_IWDG_CLK_ENABLE'I could not find such a function either in the drivers included by STM32CubeIDE in the project or in the repository in the STM32CubeIDE installation directory.This function should enable the APB peripheral clock to the Independent Watchdog (IWDG), but I couldn't find anything for this purpose anywhere in the Reset and Clock Control (RCC) registers.Does this mean that the APB peripheral clock is always active for the Independent Watchdog (IWDG) and should not be enabled? In other words, is this function unnecessary and can I comment it out?I would be grateful for any help

HiI have seen mention of STM32Cube_FW_N6_V1.3.0 being released soon, and including important fixes to demos. Is there an expected released date?

We are pleased to announce that STM32CubeProgrammer 2.21 is available What is new in 2.21: • Support for the STM32WL3Rxx microcontrollers:         – Internal memory programming        – Option byte and OTP programming        – PKCS#11        – Firmware authentication • STM32MP21x microprocessors: SSP support on Linux®• STM32WBA6xxG microcontrollers: Support for 1-Mbyte flash memory size• Support for new devices in the STM32C0 series: STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx, STM32C091xx, and STM32C092xx microcontrollers• Support for the factory reset of option bytes:        – STM32WBA5xxx and STM32WBA6xxx microcontrollers         – STM32U375/385 microcontrollers• Dynamic upgrade of components• Support for SWD multi-drop• Fast read new CLI command Main fixed issues in 2.21: Refer to the STM32CubeProgrammer wiki at: STM32CubeProgrammer errata 2.

We are pleased to announce that STM32CubeProgrammer 2.21 is available What is new in 2.21: • Support for the STM32WL3Rxx microcontrollers:         – Internal memory programming        – Option byte and OTP programming         – PKCS#11        – Firmware authentication • STM32MP21x microprocessors: SSP support on Linux®• STM32WBA6xxG microcontrollers: Support for 1-Mbyte flash memory size • Support for new devices in the STM32C0 series: STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx, STM32C091xx, and STM32C092xx microcontrollers• Support for the factory reset of option bytes:         – STM32WBA5xxx and STM32WBA6xxx microcontrollers         – STM32U375/385 microcontrollers • Dynamic upgrade of components • Support for SWD multi-drop • Fast read new CLI command Main fixed issues in 2.21: Refer to the STM32CubeProgrammer wiki at: STM32CubeProgrammer err

This page mentions that you are supposed to use tar xf for SDK extraction. Unfortunately this doesn't work for the latest SDK 6.6 (scarthgap), it looks like the SDK is just a tar archive and not compressed. $ tar xf en.SDK-x86_64-stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06.tar.gz tar: This does not look like a tar archivetar: Skipping to next headertar: Exiting with failure status due to previous errors$ tar xzf en.SDK-x86_64-stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06.tar.gz tar: This does not look like a tar archivetar: Skipping to next headertar: Exiting with failure status due to previous errors$ file en.SDK-x86_64-stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06.tar.gz en.SDK-x86_64-stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06.tar.gz: gzip compressed data, from Unix, original size modulo 2^32 934342372 gzip compressed data, unknown method, ASCII, was "", encrypted, from FAT filesystem (MS-DOS, OS/2, NT), original size modulo 2^32 93434237

Hi ST Micro,Please send me the information for the adjustable LDO output voltage desgined from R1 and R2 formula.

Hello, I am working with the STM32N6570‑DK discovery kit and using the ST Edge AI Developer Cloud to generate code for my neural network. The tool produces a project with multiple files (model, runtime, headers, etc.), but I am struggling to understand how to actually integrate this into my STM32N6 application.Specifically, I would like to know:What is the expected input format (tensor dimensions, quantization type) and how do I feed my sensor/camera data into it?How do I retrieve the output from the inference (classification vector, bounding boxes, etc.) and use it in my application logic?How should I connect the generated code with my application (main loop, data acquisition from camera/audio, etc.)?I have looked through the STM32N6 examples and documentation, but they don’t clearly explain how to bridge the generated AI code with a working application. Any guidance or pointers to documentation/examples would be greatly appreciated.Thanks in advance! 

The STM32H743XGH6 is specified to have 1 MB of Flash memory.However, it seems that the following 2 MB address ranges are writable:BANK1: 0x08000000 to 0x080FFFFFBANK2: 0x08100000 to 0x081FFFFFIf the device really has only 1 MB of Flash, I would expect the usable ranges to be:BANK1: 0x08000000 to 0x0807FFFFBANK2: 0x08100000 to 0x0817FFFFAlso, when I executed an erase operation on BANK2, it started erasing from address 0x08100000.My question is:Are the following areas valid and safe to use?BANK1: 0x08080000 to 0x080FFFFFBANK2: 0x08180000 to 0x081FFFFFAny clarification about the actual usable Flash memory area would be appreciated.

Hi,I'm trying to test and deploy this application on stm32N6-DKhttps://github.com/STMicroelectronics/STM32N6-GettingStarted-ObjectDetectionAlso follow this MOOChttps://www.youtube.com/watch?v=VV9f5e3nqM4&list=PLTJzs51NlEICI7ARAHOyUqMhTgJE0UFv0&index=8Loaded the project to stm32CubeIDE 1.19.0Can buid the project but impossible to configure or debug the application !!or this error on debug viewIf someone can help ...  

I have strange DMA problem with a F303 application, in particular a STM32F303K8 (a STM32F303x6/8 variant).The concept is relatively straightforward.A configured ADC sequence is triggered by timer, the ADC in turn triggers DMA transfers of the conversion results, and the DMA raises the TC interrupt when the specified number of transfers is reached.The problem is, the ADC almost immediately raises the OVR flag (overflow), and the DMA is disabled (CCR.EN is reset).I can't see the reason why.Detailed description of used peripherals / resources :  - ADC1_IN1, ADC1_IN2 & ADC1_IN4, 19.5 cycles, with ADC.CCR CKMODE=3 (synchronous, HCLK/4)  - TIM3 TRGO as ADC trigger (ADC1.CFGR EXTSEL=4, EXTEN = 1), at about 11kHz  - assigned DMA is DMA1 Channel 1 (see RM0316 Rev 10, table 77 at page 268)DMA is configured in circular mode, peripheral-to-memory transfer, memory increment, and half-word transfers.At the moment I try only one sequence (3 samples, i.e. half-words), instead of a l

Hello, I’m trying to flash the ST67W611 Wi-Fi module directly through UART, without using the NUCLEO host board.For hardware setup, I soldered simple tactile switches and 0.1 µF capacitors on the CHIP_EN and BOOT pins.When powering up:I press both switches to pull CHIP_EN and BOOT low (to GND).Then I release the BOOT button so that the pin is pulled up to 3.3 V through a 10 kΩ resistor.Finally, I release the CHIP_EN button, which is also pulled up to 3.3 V through another 10 kΩ resistor.After this sequence, I run the following command in Windows PowerShell, but the handshake fails:  PS D:\Backup\STM32_Project\ST67W611M1\Resource\x-cube-st67w61\Projects\ST67W6X_Utilities\Binaries> QConn_Flash\QConn_Flash_Cmd.exe --port COM8 --config NCP_Binaries\mission_t02_flash_prog_cfg.ini --efuse=NCP_Binaries\efusedata.bin Here is the full output log:  [00:05:40.891] - Serial port is COM8 [00:05:40.891] - ================================================== [00:05:40.8

I saw some older threads regarding this issue, but no way to fix this?