Issue with MIPI DSI Video Mode and SN65DSI83 Bridge on STM32H747

[siddum]

Dear ST Community,

We are currently working on the STM32H747 controller using the MIPI DSI interface in video mode.

In our setup, we are using the SN65DSI83TPAPRQ1 bridge to convert MIPI DSI signals into LVDS signals for our display panel.

The MIPI configuration and bridge configuration details are attached below.

After configuring the CSR registers on the bridge side, we are reading Register 0x0A and Register 0xE5 for status verification, as specified in the SN65DSI83TPAPRQ1 datasheet initialization sequence.

We have also enabled the test pattern, and the display turns ON (screenshot attached below).

Observations:

• For Register 0x0A, bit 7  is not reading as 1

• For Register 0xE5, the expected value is 0x00, but it is reading as 0x01

• We are observing clock signals at the bridge output

• However, no data signals are present on the LVDS side

Queries:

• What could be the reason for bit 7 not being set in Register 0x0A?

• What does Register 0xE5 reading 0x01 instead of 0x00 indicate?

• Does this behaviour suggest an issue with DSI data lane activity or configuration?

• Are there any additional requirements or configurations needed for DSI video mode on STM32H747 to ensure proper data transmission?

We kindly request you to review this and provide your guidance or debugging suggestions.

Thank you for your support.

Best regards,
Siddu M.

[Peter BENSCH]

This issue is mainly on the bridge side.

The STM32H747 only provides the DSI video stream and configures the SN65DSI83 via I2C. Since the bridge’s test pattern works, basic panel power‑up and I2C seem to be OK. The meaning of reg 0x0A bit 7 and reg 0xE5 = 0x01 is specific to TI and most likely indicates that the bridge does not detect a valid DSI video input (timing / lane / format mismatch, PLL, etc.).

On the STM32 side, please just re‑check:

• DSI video timings (h/v active, porches, sync, totals)
• lane count and bit rate
• pixel format (RGB888 vs RGB565, etc.)
• video mode configuration (continuous clock if required)

For the exact status‑bit meaning and detailed debug, the TI support and documentation for SN65DSI83 should be the correct reference.

Regards
/Peter