I'm trying to configure the S2-LP with the following settings:
- Base frequency: 915 Mhz;
- Modulation: ASK (modulation depth 90%, '1'=10dBm and '0'=0dBm);
- Data rate: 80kHz;
- Channel space: 389kHz;
- Channel: 0.
I've developed a HAL because using the X-CUBE-SUBG1 or X-CUBE-SUBG2 is not an option given the need of offloading MCU. What I managed to do was controlling S2-LP with a custom board using STM32G030K6 SPI1 (4Mbps) + DMA1 (TX and RX) with frame queuing treated by TIM14 (start and end of frames spaced by 50us), transmission and reception via FIFO (my application requires custom packet). The RF section is the same as STEVAL-FKI868V2. Enter and exit S2-LP states works as expected (checked through debugging and with a Saleae Logic 8 logic analyzer), but the problem is that PA in TX mode only provides -50dBm (measured with a Rhode & Schwarz FPC1500 on the SMA connector, image bellow) with a noise level of -95dBm. Configuring PA above 10dBm only works once... The next time it enters TX, no output signal is present.
Is there an example with S2-LP using ASK? Also, using the the equation in X-CUBE-SUBG2 for PA output doesn't seem to work, as the power is always the same: PA_LEVEL = 25 - 2 * power_output[dBm]. I believe some setting is, but it's hard to know because S2-LP datasheet lacks information.
I'm configuring S2-LP in STANDBY mode with these values, following "S2-LP bring-up good practices" from EMEA RF support team presentation:
/* Frame has the format:
* static const u8 frame[] = { size_of_frame, 1st_SPI_byte, 2nd_SPI_byte, ... }
*/
static const u8 cfg0[] = { 6, 0x00, 0x00, 0x02, 0xA2, 0xA2, 0xA2 }; /* GPIO[0:3]_CONF: GPIO0 = IRQ, retante = GND*/
static const u8 cfg1[] = { 8, 0x00, 0x05,
0x42, 0x49, 0x99, 0x99, /* SYNT[3:0]: fbase = 915MHz */
0x2F, 0xC2 /* IF_OFFSET_ANA + IF_OFFSET_DIG: for XTAL = 50MHz */
};
static const u8 cfg2[] = { 15, 0x00, 0x0C,
0xFF, 0x00, /* CHSPACE + CHNUM: ch_space = 389kHz, ch_num = 0 only fbase */
0x00, 0x27, 0x5F, 0x83, 0x93, /* MOD[4:0]: ~80kbps ASK */
0x23, /* CHFLT: double-sided bandwidth ~100kHz */
0xC0, 0x18, 0x23, /* AFC[2:0]: optimization for OOK+ASK */
0xE7, 0x56 /* RSSI_FLT + RSSI_TH: dynamic 18dB threshold, dbm = TH - 146 */
};
static const u8 cfg3[] = { 10, 0x00, 0x1A,
0x00, 0x10, 0x42, 0x59, 0x82, /* AGCCTRL[4:0]: for OOK/ASK */
0x45, /* ANT_SELECT_CONF */
0x28, 0x28 /* CLOCKREC[2:1]: for OOK/ASK */
};
static const u8 cfg4[] = { 10, 0x00, 0x2B,
0x00, 0x00, 0x00, 0x10, 0x00, 0x04, /* PCKTCTRL[6:1]: TX and RX through FIFO */
0xFF, 0xFF /* PCKTLEN[1:0]: max size 65535 bytes */
};
static const u8 cfg5[] = { 20, 0x00, 0x3A,
0x00, 0x00, /* PROTOCL[1:0]: disabled */
0x60, 0x20, 0x60, 0x20, /* FIFO_CONFIG[3:0]: almost full = 96, almost empty = 32 */
0x40, /* PCKT_FLT_OPTIONS: OR logic for RX timeout */
0x00, 0x00, 0x00, 0x00, 0x00, /* PCKT_FLT_GOALS[4:0]: disabled */
0x01, 0x00, 0x01, 0x00, 0x01, 0x00 /* TIMERS[5:0]: default */
};
static const u8 cfg6[] = { 13, 0x00, 0x54,
0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, 0x0D, /* PA_POWER[8:1] : PA '1'=6dBm, until now only OOK works */
0xC0, /* PA_POWER0: PA no ramp */
0x03, 0x8B /* PA_CONFIG[1:0]: PA with filter */
};
static const u8 cfg7[] = { 3, 0x00, 0x65, 0xD0 }; /* SYNTH_CONFIG2: for XTAL = 50MHz */
static const u8 cfg8[] = { 3, 0x00, 0x68, 0x03 }; /* VCO_CONFIG: for XTAL = 50MHz */
static const u8 cfg9[] = { 4, 0x00, 0x6C, 0x45, 0x00 }; /* XO_RCO_CONF[1:0]: for XTAL = 50MHz, Gm = 13,2mS */
static const u8 txc0[] = { 3, 0x00, 0x39, 0x00 }; /* PROTOCOL2: TX FIFO */
static const u8 txc1[] = { 6, 0x00, 0x50, 0x00, 0x00, 0x01, 0x00 }; /* IRQ_MASK[3:0]: TX FIFO almost empty */
static const u8 txc2[] = { 7, 0x00, 0x75, 0x17, 0x9B, 0xF4, 0x39, 0x72 }; /* PM_CONF[4:0]: p/ XTAL = 50MHz, SMPS = 1,8V and TX = 5,46MHz */
static const u8 rxc0[] = { 3, 0x00, 0x39, 0x04 }; /* PROTOCOL2: RX FIFO */
static const u8 rxc1[] = { 6, 0x00, 0x50, 0x00, 0x00, 0x02, 0x00 }; /* IRQ_MASK[3:0]: RX FIFO almost full */
static const u8 rxc2[] = { 7, 0x00, 0x75, 0x17, 0x8F, 0xF9, 0x39, 0x32 }; /* PM_CONF[4:0]: XTAL = 50MHz, SMPS = 1,4V and RX = 3,125MHz */
/* Queue sequence to configure TX */
static const u8 *config[] = { cfg0, cfg1, cfg2, cfg3, cfg4, cfg5, cfg6, cfg7, cfg8, cfg9, txc0, txc1, txc2 };
/* Queue sequence to configure RX */
static const u8 *config[] = { cfg0, cfg1, cfg2, cfg3, cfg4, cfg5, cfg6, cfg7, cfg8, cfg9, rxc0, rxc1, rxc2 };