STM32 MPUs Products and hardware related

Hi!I'm looking for an appropriate DRAM for the MP257.I know there is a table about validated DRAM for MPUs.https://wiki.st.com/stm32mpu/wiki/Validated_DRAM_on_STM32_MPU_portfolioMy question is if there is a DRAM standard i csn follow if I want to try another vendor of DRAM?I'm looking for other types of DRAM that shares the same footprint and connection. But I'm unsure if it's good enough to select a DRAM on those specifications.I've heard that there is a standard called JEDEC. If another vendor follows that standard, does that mean that this DRAM is compatible with the MP257?For example: The MP257-DK is validated with MT53E1G32D2FW-046 WT:C, but that DRAM is out of stock. Could I use MT53E1G32D2FW-046 WT:B instead? It's the design B version instead of design C version.

How may I use STM32MP257F-EV1 PCIe in *Endpoint Mode*?  I am looking to connect two STM32MP257F-EV1 devices together via PCIe; one device in PCIe host mode, and the other in PCIe endpoint mode.1) Physical connectionAccording to the boards user manual, I see that the PCIe interface is presented on CN13 and described as a Mini-PCIe.  How can I connect two STM32MP257F-EV1 devices together via PCIe?2) Clock configurationSection 8.9.1 talks about a 100MHz Ref Clock options.  There appear to be three options: (1) SOC generates a clock, (2) SOC takes external clock from U33, or (3) SOC takes clock from the mini-PCIe connector.  The selection of an option refers to several "R###" on/off choices.  Are these choices made by adjusting surface mount resistors?If we aim to connect one eval board ("Host mode") to another ("Endpoint mode"), should we aim to bring bring board's clock to the other?  Or provide same external clock to both boards?Where is this exte

ProductSTM32MP257DAK3 CPUBoard: Custom board (based on STM32MP257)Software EnvironmentU-Boot: from stm32mp-openstlinux-6.6-yocto-scarthgap-mpu-v25.08.27Boot stage: U-BootDisplay command: bmp displayDisplay interface: MIPI-DSIProblem DescriptionI am using STM32MP257DAK3 with two different MIPI-DSI LCD panels:Panel A: MIPI-DSI 4 lanes→ Works correctly in U-Boot using bmp displayPanel B: MIPI-DSI 1 lane→ Does NOT work in U-Boot using bmp displayAccording to the STM32MP25 reference manual, the DSI_PCONFR register supports lane configuration from 1 to 4 lanes.Therefore, I expect DSI 1-lane mode to be supported by hardware.However, in U-Boot, the 1-lane panel does not display anything. Important ClarificationFor both panels:Device Tree is already adapted separately:Correct dsi,lanes = <4> and dsi,lanes = <1> configurationSeparate panel nodesPanel drivers are already adapted and validatedQuestion / Clarification RequestedI would like to confirm:Does the U-Boot DSI driver (dri

Hi Team,Does STM32MP257F-DK supports OpenSTDroidIf supports where can i find the starter package for this Discovery board.

I just need to confirm something. I read in the RM Document that STM32MP157 does not support ODT for LPDDR3 SDRAM but it does have a DDR Controller and PHY which supports LPDDR3. I just wanted to know if I can freeze LPDDR3 for my case? I suppose not giving ODT simply means that I need to provide termination on the PCB itself right? Can someone please throw some more light on this? It would be good to have some reference as well.

Hello,ST has released the STM32MP1 and the newer STM32MP2 series of MPU products. I would like to know what the roadmap looks like after the STM32MP2.Is there any information available about the next-generation STM32 MPU family (e.g., a potential STM32MP3 or a new architecture)?Any official hints or timelines would be greatly appreciated.Thank you.

Dear all:I am currently using the distribution version:V5、rt 6.1.82-rt patch、stm32mp257Prompt in Wiki，need disable CONFIG_CPU_IDLE，But in reality, it cannot be closed.Why am I paying attention here? Because I encountered an Oops exception during running.login: [ 370.478552] BUG: scheduling while atomic: swapper/1/0/0x00000002 [ 370.478575] Modules linked in: cfg80211 rfkill stm32_adc stm32_timer_trigger stm32_lptimer_trigger mcp251xfd crct10dif_ce nvme nvme_core stusb160x typec stm32_adc_core stm32_crc32 spi_stm32 m_can_platform m_can can_dev cdc_acm optee_rng rng_core sch_fq_codel 8021q garp mrp bridge stp llc sch_prio ch343(O) acm(O) edgx_pfm_lkm(O) stm32_deip(O) ip_tables x_tables ipv6 [ 370.478682] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G O 6.1.82-rt27 #1 [ 370.478691] Hardware name: MYiR STM32MP257x Evaluation Board 2 (DT) [ 370.478696] Call trace: [ 370.478700] dump_backtrace+0xdc/0x130 [ 370.478720] show_stack+0x18/0x30 [ 370.478731] dump_stack_lvl+0x64/0x80 [ 370.478742] dump_s

I've got a custom board built around an STM32MP135AAE3.  It's designed to have an eMMC instead of an SD card, the problem is that the board was not laid out correctly and the JTAG isn't connected.I'm having trouble writing to the eMMC (that's another topic) but I'm trying to make some progress while waiting for a board spin.  The board is in serial boot mode so I'm able to upload bootloaders, am I allowed to upload any arbitrary program and call it a bootloader?  I'm thinking I could start testing board features by uploading small programs to test the board if that's allowed with a "bootloader". 

Hello ST Community,Custom STM32MP2 board with STM32MP257FAK fails rootfs mounting from eMMC in HS200 (CRC errors), works at 52MHz DDR.In the device tree side only difference is removing HS200 property and added Max frequency to 52Mhz.&sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; non-removable; no-sd; no-sdio; st,neg-edge; bus-width = <8>; vmmc-supply = <&scmi_vdd_emmc>; vqmmc-supply = <&scmi_vddio2>; mmc-ddr-1_8v; max-frequency = <52000000>; status = "okay"; };Attached hs200 issue Log How to debug further to work with hs200?

Hi everyone,we applied the ST FWU reference solution on our own platform based on the STM32MP157F.The solution was taken and adapted from the ST Yocto layer meta-st-ota (https://github.com/PRG-MPU-CUST/meta-st-ota).We have a few questions to clarify the default behavior:What is the default behavior in the early boot stage Do we understand correctly that fsbl1 and fsbl2 are intended to contain identical TF-A images for fail-safe purposes, and that the ROM looks for the first valid FSBL (starting from fsbl1) and loads it?Rollback behavior at ROM / TF-A layerIs it correct that there is no FWU rollback concept implemented in ROM / TF-A itself?I.e. fsbl1 is not treated as part of a bank like [fip-a, bootfs-a, rootfs-a], but instead the two FSBL slots are only there to allow a second try to load the same TF-A version from fsbl2 if fsbl1 fails?Updating TF-A over-the-airIf we decide to update TF-A via OTA (with RAUC and the ST FWU solution), do we understand correctly that:TF-A needs to b

Hello,We have designed a custom board based on the STM32MP157F-DK2 platform.The design uses the STM32MP157FAC MPU and includes the following peripherals:MicroSD (SDMMC)STPMIC1 PMICDDR3L memoryEthernetUART4 for console My power sequencing, PMIC wiring, and clock architecture are identical to the DK2 reference schematics.All voltage rails appear stable except the DDR rails, and SDMMC signals look correct during boot.However, when I try to boot from the SD card and monitor UART4, I only receive the following messages:PANIC at PC : 0x2ffeada7Exception mode = 0x00000016 at : 0x2ffeada7There is nothing else printed afterward. From the Cortex-A7 exception codes, 0x16 indicates an Undefined Instruction exception, and the address 0x2FFEADA7 lies inside the SYSRAM area. This suggests the crash happens very early, likely during TF-A execution.My problem is that the MPU never seems to wake up properly, and I cannot identify the exact origin of the failure.I would appreciate guidance on w

The board was designed incorrectly, they have pins for a JTAG but forgot to actually route them to the MPU.  The eMMC is not going to have a first-stage bootloader on it, and it's looking like it's not possible to flash an SPL to the eMMC over USB alone?  Management won't be happy to do another board spin but it's sure looking like that's the only path forward.ChatGPT says:USB DFU alone cannot flash first-stage bootloader (SPL) to eMMC on a totally blank STM32MP135.This is not a dfu-util bug — it’s how the STM32MP1 ROM works.You need hardware access to write SPL + U-Boot to eMMC:Option A: SWD / JTAG (ST-LINK)CubeProgrammer can directly write SPL + U-Boot to eMMC.Option B: SD card bootThe ROM can load a SPL + U-Boot image from SD into RAM and then copy it to eMMC.

In AN5489, the HSE is recommended to have 40 MHz. Why 40 MHz?Why not 24 MHz HSE? Is 40 MHz a specific value for a certain pheripherial?

Hi,I am new at STM32MP2. I have a stm32mp25f-ev1 board and I was able to build the distribution package and to run it on the board.My next step is to build an image for my own board that was designed using the eval board as a reference, but with many changes in pins (except the eMMC and SDCARD).I am strugling for 2 weeks now to get this working. I tried to follow the instructions from the wiki but could not get it up and running. Then I started to improvise (chat gpt, google, ...)... What I did was to create a new layer under layers. This layer should be based on the meta-st-stm32mp layer and have no additions. So I thought it would use the same devicetree as the meta-st-stm32mp layer. Then I created a machine in this layer. The machine is just with a new name but no devicetree changes. After that I built a new configuration using this layer.The idea was to get to somthing working on the eval board before I start adjusting it to my board. While building I got these warnings:W

Hi I was trying to connect a custom LVDS display to my STM32MP257F-dk board but it does not seem to work, The display has a resolution of 1024x600 pixel and also it uses "vesa-24" scheme, so i assume that i don't need to change the device tree as it matches the specification of the default display which is supplied with the dev kit. If otherwise please advice. Please not that i am not using the touch panel of the display so the i2c connection of the dev kit are not connected to the display board can that disable the LVDS port ? Is there any way to debug the LVDS display, Please advise in this matter. Regards,Samip

It seems Azure® RTOS might be able to run on STM32MP135AAE3, the "Introduction to Azure RTOS with STM32" says "All STM32MP13x lines are covered by default by Azure® RTOS middleware within the matching STM32Cube MPU packages" but I'm having trouble finding any examples or "getting started" guides. 

I've inherited a custom board that contains (among other things) an STM32MP135AAE3, an eMMC, and an Ethernet controller (DP83826ERHBR).  No SD card, no HDMI, no keyboard.  For that matter, no JTAG (board error). I had thought about running Zephyr but it's looking like that's not currently possible (discussion here).The documentation for creating a Linux image for this chip seem to fall under two categories:1) If you are using one of the development kits, here are explicit step-by-step instructions that will make it a joy2) If not, here (thud) are the manuals for yocto, bitbake, repo, and really the entire Linux kernel.  Read them all, digest them completely, and the answer will be obvious.Am I missing something?  Are there instructions somewhere to help me create a Linux image?  I don't need to become a yocto expert, I just need to create one Linux image one time.Thanks,Chris 

The STM32MP135AAE3 board was designed incorrectly, they have pins for a JTAG but forgot to actually route them to the MPU.  The eMMC is not going to have a first-stage bootloader on it, and it's looking like it's not possible to flash an SPL to the eMMC over USB alone?  Management won't be happy to do another board spin but it's sure looking like that's the only path forward.

I'm using a custom board, and use  the optee device tree generated by STM32CUBEMX and full UART log. Panic at core/kernel/dt_driver.c:904 <probe_dt_drivers>. How to solve this problem?

I'm facing a problem when trying to build an image for my mp257f-eval board using a custom device tree generated from cubemx. I've followed the instructions from the following wiki : https://wiki.st.com/stm32mpu/wiki/How_to_compile_the_device_tree_with_the_Distribution_Package#Creating_a_new_open_embedded_layer_for_your_demo But the build fails when trying to compile optee, because the device tree does contains a reference for a pll device not declared earlier. i did some lookups inside the working directory, and i found it declared in the recipes-security/optee folder under meta-st-stm32mp meta layer (https://github.com/STMicroelectronics/meta-st-stm32mp/blob/scarthgap/recipes-security/optee/optee-os/0001-4.0.0-stm32mp-r2.patch). i guess the patch is not applied to the device tree, only the standard device trees for common boards get patched. i don't know if someone has faced a similar problem and can help? I'll attach the log and configs files using for the build. thanks in advance.T

Hello everyone,I'm experiencing an issue with network packet loss in a setup using the AR8031 PHY with an STM32MP1 system and would appreciate any insights or suggestions.Problem Description:Significant (60-90%) packet loss when STM32MP1 board is directly connected to a Linux host via EthernetNo packet loss when the same board is connected through an Ethernet switchIssue occurs consistently with direct host connectionsTested/Verified so far:Multiple known-good Ethernet cables (CAT5e/CAT6)Different Linux hostsLink speed and duplex settings (100M/1G, full/half duplex), 100M works fine with no packet lossEnable/disable various PHY driver quirks (qca,disable-smarteee, qca,disable-hibernation-mode, qca,clk-out-strength, qca,keep-pll-enabled, qca,smarteee-tw-us-1g)Device Tree Snippet:&ethernet0 { status = "okay"; pinctrl-0 = <&ethernet0_rgmii_pins_a>; pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; ph

My freshly arrived and assembled STEVAL-ROBKIT works well in Autonomous and Follow-Me mode but not in Drive. Nor does the "lock" toggle seem to do anything.  Lock does not stop Follow-Me if activated.  Any ideas?John FergusonSt Petersburg, FL

Hi everyone,I need some guidance on building a real-time face recognition pipeline on the STM32MP2 platform.My requirements:Reliable face detectionGood, consistent face embeddingsDecent FPS on MP2Preferably ONNX or pure CPU, since heavy frameworks aren’t idealMinimal external dependenciesNo reliance on TensorFlow or PyTorchI’m looking for suggestions on:Which face detector works best on MP2 (YUNet / SCRFD / BlazeFace / SSD)?Which embedding model (ArcFace, MobileFaceNet, SFace, etc.) performs well on CPU?Any recommended ONNX + OpenCV DNN pipelines that others have successfully run on MP2?Tips for optimizing inference speed on this hardwareIf anyone has experience or working examples, it would really help me understand the right direction to build a practical, efficient solution.Thanks in advance!

Hi!I am working on a custom board design based on STM32MP157FAA1.I need to interface a MIPI display with the microprocessor.I am powering this microprocessor using STPMIC1APQR PMIC. As per the datasheet of the PMIC, the default output voltage from BUCK3 will be 3.3V and this powers VDD_DSI (Pin A14) and I am also aware that the microprocessor internally generates 1.2V for DSI section.Now the MIPI display I'll be using utilizes EK79007 LCD driver IC. The recommended VDD for EK79007 is 1.8V. I want to know if this display can be interfaced with the MIPI section of STM32MP157FAA1.I have added the data sheet of the display and also the LCD driver for your reference.Thanks & Regards,Cleatus Wesley

How can I build the M33TD Yocto images from sources?stm32mp2-m33td-openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11 I managed to build the A35 flavor following this excellent summary:Solved: stm32mp257f-EV1 yocto - STMicroelectronics Community But now I would like to do the same for the M33TD boot mode. My board is a STM32MP257F-EV1