STM32 MPUs

Hi,Could you share documentation or examples for running quantized foundational models (e.g. Google Gemma) on the STM32MP257F-DK—first in Python, then in C/C++ using the STM32MP2 NPU? Specifically:Does the STM32MP2 NPU support transformer-based architectures, or is it limited to CNNs (like the STM32N6)?Which inference frameworks are supported for GenAI on this platform? does this NPU ported by ST for llama.cpp ?Sorry, couldn't find required info from STM32 MPU wiki pages.Thanks!  

I've inherited a board that is based on an STM32MP135AAE3 and has an external DDR (W63AH6NBVABI, a DRAM 1Gb LPDDR3 from Winbond).  It appears I need to create a DDR.h file similar to the stm32mp13xx-ddr3-4Gb.h or stm32mp13xx-ddr3-8Gb.h files that STM provides (right?)   I've taken the existing stm32mp13xx-ddr3-4Gb.h and am slowly going through, figuring out exactly what each line needs and then trying to track down the appropriate information from the DDR datasheet.  My biggest concern is that I get the timing ALMOST right and end up with a DDR that works 99.99% of the time (failing, of course, only at customer sites). 1) Is there an archive of DDR definition files somewhere that I missed?2) Is there a better way to generate this DDR definition file?3) Is there a way to test I did it right besides running various memory tests for days and days? As an example, this file needs information like this:// DDRCTRL SDRAM timing regist

Dear Team,We are trying boot Uboot(V2025.04) on a Custom board with STM32MP157AAA3 Processor.But while booting we can see that code hangs at WDT: started Watchdog@5a002000 with servicing every 1000ms (32s timeout) and restart after sometime.We have attached the screenshot for the reference Thanks & RegardsAkshitha Pattem   

Hello We are implementing the memory CRC generation sequence as described in the reference manual. According to the documented procedure, the following steps must be executed:1. Write 0x0 in CRCC[1:0] of RAMCFG_xCCR1 to deactivate the CRC.2. Write 1 in SRAMHWERDIS of RAMCFG_xCR to disable the hardware erase.3. Select the buffer size to take into account during the CRC computation by settingCRCBS[2:0] in RAMCFG_xCCR1.4. Write 0x1 in CRCC[1:0] of RAMCFG_xCCR1 to activate the CRC.5. Write 1 in CRCCS of RAMCFG_xCCR2 to start the CRC computation.The calculated signature is stored in RAMCFG_xCCSR when CRCEOC is setin RAMCFG_xCSR.While following this sequence, the CRCEOC flag never becomes set. We have attached the code segment used to trigger the CRC operation and to subsequently start the Cortex-M33 boot process. Could you please review the implementation and confirm whether the initialization flow is correct?void ConfigRetram(void){/********************** 1 Enable ECC*****************

Hi ST Team,I am working with STM32MP257F-EV1 board and facing an issue while trying to connect the ST-Link interface using STM32CubeProgrammer.Connection setup:An external ST-LINK/V2 programmer is connected to the CN22 (ST-LINK header) on the STM32MP257F-EV1 board.Behaviour:1) Tried connecting with both SWD and JTAG modes, but the connection fails in both the cases.2) The board is detected only when connecting USB to connector CN15(USB_DRD) in DFU Mode.For your reference ,I have attached the STM32CubeProgrammer configuration screenshots and connection logs.Additionally, while reviewing the ST Community forum, I found the following discussion related to this issue.link: https://community.st.com/t5/stm32-mpus-software-development/debug-authentication-on-the-stm32mp2257f-ev1-for-st-link/td-p/708255Could you please confirm whether this behavior is expected for the STM32MP257F-EV1 and any configuration or steps to enable and validate CN22 (ST-LINK header) on STM32MP257F-EV1 board ?Thanks an

I'm trying to use pwm for backlight control in stm32mp257f-ev1, the same changes shown in below patch is implemented in both u-boot and kernel, i used u-boot pwm commands and it seems working but im getting this deferred probing issue in kernel logs and display turns of when entering kernel.Im in midddle of board bring up hoping for a quick reply, thanks in advance.This is the kernel log[ 0.268819] /soc@0/bus@42080000/display-controller@48010000: Fixed dependency cycle(s) with /soc@0/bus@42080000/lvds@48060000 [ 0.295408] /soc@0/bus@42080000/lvds@48060000: Fixed dependency cycle(s) with /soc@0/bus@42080000/display-controller@48010000 [ 0.308304] /soc@0/bus@42080000/display-controller@48010000: Fixed dependency cycle(s) with /soc@0/bus@42080000/lvds@48060000 [ 0.338635] /soc@0/bus@42080000/lvds@48060000: Fixed dependency cycle(s) with /soc@0/bus@42080000/display-controller@48010000 [ 0.352683] /soc@0/bus@42080000/display-controller@48010000: Fixed dependency cycle(s) with /soc@0/bus@420

Hello Everyonelinux kernel version: 6.6.78After configuring the device tree, I can see the SPI device /dev/spidev6.0 on the STM32MP257F-DK board. However, when I run spidev_test[1], it returns the error message "Invalid argument."I tried using an oscilloscope to measure the signals on the CLK, MOSI, and MISO pins separately, but no signals were detected.Please give me some suggestions to help me fixed it. Thanks in advance.//------------------------------------------------------------------------------------------------------the SPI device tree setting as following:Path:~/STM32MPU-Ecosystem-v6.6/Developer-Package/BSP/sources/ostl-linux/linux-stm32mp-6.6.78-stm32mp-r2-r0/linux-6.6.78/arch/arm64/boot/dts/st/stm32mp257f-dk.dtsaliases { serial0 = &usart2; serial1 = &usart6; serial2 = &usart1; ethernet0 = &eth1; spi6 = &spi6; }; &spi6 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi6_pins_a>; pinctrl-1 = <&spi6_sleep_pins_a>

Hi We have a custom board using STM32MP257F and would like to program external NIOR flash using STM Cube programmer over a UART interface.We have the following modified TSV file, where we have modified the first line to use - 0x01 fsbl-boot Binary none 0x0 arm-trusted-firmware/tf-a-stm32mp257f-ev1-cm33tdcid-ostl-serial-ca35tdcid-optee-programmer-uart.stm32- 0x02 fip-ddr FIP none 0x0 fip/fip-stm32mp257f-ev1-cm33tdcid-ostl-serial-ca35tdcid-ddr-optee-programmer-usb.bin- 0x03 fip-boot FIP none 0x0 fip/fip-stm32mp257f-ev1-cm33tdcid-ostl-serial-ca35tdcid-optee-programmer-usb.binDo we also need to modify the second and third lines to use a UART version of the FIP files? We cannot find these files in our distribution, we only have ones with xxx-usb.bin.How can we proceed?  

Hello,I am working on a custom board derived from the STM32MP157F-DK2 reference design and currently validating the basic bring-up.I have a few questions specifically related to the Cortex-M4 (MCU) core on STM32MP157F:Checking MCU execution via JTAG/SWDUsing the JTAG/SWDIO pins, how can I confirm whether the Cortex-M4 core is running or halted?Are there recommended tools or procedures (e.g., STM32CubeProgrammer, OpenOCD, ST-Link) to attach to the M4 core independently of the A7 cores and verify execution status? MCU startup code responsibilityDoes the Cortex-M4 require a separate startup/application binary (startup code, linker script, vector table), or is this handled automatically as part of the Yocto/OpenSTLinux build?In other words, does Yocto provide and load a default M4 firmware, or is it expected that we build and deploy an M4 firmware separately (for example using STM32CubeIDE)? Boot flow clarificationAt what stage is the M4 core released from reset?Is this controlle

I have CubeMX 2.0.0 and I notice that if I want to enable DSIHOST, I need to first enable HSE.But the clock configuration of the DSI does not require HSE. It seems that the clock configuration of DSI seems to work with HSI in CubeMX 2.0.0.So, the question is: I need to enable HSE, but do I need to clock configure it for DSI as well? Or could I use HSI in the clock configuration, even if HSE is enabled? Processor: STM32MP257FAK3 

Hi!I'm looking for an appropriate DRAM for the MP257.I know there is a table about validated DRAM for MPUs.https://wiki.st.com/stm32mpu/wiki/Validated_DRAM_on_STM32_MPU_portfolioMy question is if there is a DRAM standard i csn follow if I want to try another vendor of DRAM?I'm looking for other types of DRAM that shares the same footprint and connection. But I'm unsure if it's good enough to select a DRAM on those specifications.I've heard that there is a standard called JEDEC. If another vendor follows that standard, does that mean that this DRAM is compatible with the MP257?For example: The MP257-DK is validated with MT53E1G32D2FW-046 WT:C, but that DRAM is out of stock. Could I use MT53E1G32D2FW-046 WT:B instead? It's the design B version instead of design C version.

Hi ST Team,I am working on custom MPU board based on STM32MP257F-EV1 reference design.For our design,reassigned I2C1 from the M33 core to the A35 core using STM32CubeMX.The I2C1 ownership changed from CID2 (M33) to CID1 (A35) in CubeMX.Corresponding RIF changes are applied in stm32mp257f-ev1-ca35tdcid-ostl-rif.dtsi and enabled I2C1 entry in linux devicetree with clock frequency 400kHz.During runtime, I2C1 SCL frequency is observed at ~141 kHz, even when:clock-frequency = 400000clock-frequency = 100000On referring clock configuration section in cubeMX, could observe the PLL4 is the parent clock for both I2C1 and I2C2.I2C2 clock output matches the configured frequency on hardware probing in both frequency (100 and 400kHz).Whether any additional clock, RIF, or access-controller configuration is required specifically for I2C1 after moving it to the A35 core.Can you please check and help us to resolve the issue.BSP - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06 - distribution packageThanks

How may I use STM32MP257F-EV1 PCIe in *Endpoint Mode*?  I am looking to connect two STM32MP257F-EV1 devices together via PCIe; one device in PCIe host mode, and the other in PCIe endpoint mode.1) Physical connectionAccording to the boards user manual, I see that the PCIe interface is presented on CN13 and described as a Mini-PCIe.  How can I connect two STM32MP257F-EV1 devices together via PCIe?2) Clock configurationSection 8.9.1 talks about a 100MHz Ref Clock options.  There appear to be three options: (1) SOC generates a clock, (2) SOC takes external clock from U33, or (3) SOC takes clock from the mini-PCIe connector.  The selection of an option refers to several "R###" on/off choices.  Are these choices made by adjusting surface mount resistors?If we aim to connect one eval board ("Host mode") to another ("Endpoint mode"), should we aim to bring bring board's clock to the other?  Or provide same external clock to both boards?Where is this exte

I am trying to create custom sd card image for the stm32mp157f-dk2 board. For device tree I used dts files from basic project created by STM32CubeIDE for that board, for now I didn''t do any changes to device tree. I used latest sources from v.25.08.27 and sdk v.25.06.11 to build kernel, modules and all required loaders.But when I try to flash sd card with created loaders, STM32CubeProgrammer gets stuck on trying to reconnect to the board over USB connection:10:21:44 : STM32CubeProgrammer API v2.20.0 | Linux-64Bits10:22:15 : Read TSV File: /home/ivan/workspace/DeviceTree/FIP_artifacts_MP1/FlashLayout_sdcard_p6_mp1-optee.tsv10:22:15 : Number of partitions: 1310:22:28 : USB speed : High Speed (480MBit/s)10:22:28 : Manuf. ID : STMicroelectronics10:22:28 : Product ID : DFU in HS Mode @Device ID /0x500, @Revision ID /0x000010:22:28 : SN : 00270035313351173534343110:22:28 : DFU protocol: 1.110:22:28 : Board : --10:22:28 : Device ID : 0x050010:22:29 : Start Embedded Flashing service10:22

Hello! I'm working on bringing up a bare-metal STM32MP133C bare-metal on the dev kit from DIGI, using the HAL layer from ST. The problem I'm running in to is we're getting stuck on HAL_ETH_Init as when we enable the MAC clock, DMAMR's 0 bit (the reset bit) is stuck at 1, causing a timeout.  From reading the reference manual, all related clocks need to be enabled for the reset to work, so I'm operating under the assumption there's a clock issue. I've initialized/configured the peripheral clock for PLL4, I'm enabling the relevant GPIO clocks, along with the ethernet clocks ETH1CK, ETH1TX, ETH1RX, and ETH1MAC. This leads me to believe the issue may be with the PHY clock. As we're using the Marvell PHY that comes with the board, I've (attempted) to set it so the PHY uses PLL4 by changing the appropriate bits in syscfg's PMCSETR.  I figured that would be enough to get it all going... but it still seems I'm missing something. I've tried generating the code from CubeMX to

Hello,I can’t download the file en.SOURCES-stm32mp-openstlinux-6.6-yocto-scarthgap-mpu-v25.08.27.tar.gz from https://www.st.com/en/embedded-software/stm32mp1dev.html#get-software. Only this file gets downloaded: SDK-x86_64-stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06.tar.gz.Could you please advise how I can download the correct en.SOURCES?

Hello community!I am trying to port a firmware for a Seeed Odyssey SOM-based board from Hardknott to Mickledore. This uses meta-st-odyssey and meta-st-stm32mp (openstlinux-6.1-yocto-mickledore-mpu-v24.06.26). I have it booting fine on the development board, but hanging on the production hardware, which re-muxes quite a few pins. The switch to Mickledore also meant I had to switch from the trusted to the optee boot scheme. It hangs always after listing the clocks:NOTICE: CPU: STM32MP157CAC Rev.BNOTICE: Model: ******INFO: PMIC version = 0x20INFO: Reset reason (0x214):INFO: IWDG2 Reset (rst_iwdg2)INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe2000INFO: FCONF: Reading firmware configuration information for: stm32mp_ioINFO: FCONF: Reading firmware configuration information for: stm32mp_fuseINFO: Using SDMMCINFO: Instance 1INFO: Boot used partition fsbl1NOTICE: BL2: v2.8-stm32mp1-r2.0(debug):lts-v2.8.15-dirty(567af710)NOTICE: BL2: Built : 00:51:33, Jan 26 2024INFO: BL2: D

ProductSTM32MP257DAK3 CPUBoard: Custom board (based on STM32MP257)Software EnvironmentU-Boot: from stm32mp-openstlinux-6.6-yocto-scarthgap-mpu-v25.08.27Boot stage: U-BootDisplay command: bmp displayDisplay interface: MIPI-DSIProblem DescriptionI am using STM32MP257DAK3 with two different MIPI-DSI LCD panels:Panel A: MIPI-DSI 4 lanes→ Works correctly in U-Boot using bmp displayPanel B: MIPI-DSI 1 lane→ Does NOT work in U-Boot using bmp displayAccording to the STM32MP25 reference manual, the DSI_PCONFR register supports lane configuration from 1 to 4 lanes.Therefore, I expect DSI 1-lane mode to be supported by hardware.However, in U-Boot, the 1-lane panel does not display anything. Important ClarificationFor both panels:Device Tree is already adapted separately:Correct dsi,lanes = <4> and dsi,lanes = <1> configurationSeparate panel nodesPanel drivers are already adapted and validatedQuestion / Clarification RequestedI would like to confirm:Does the U-Boot DSI driver (dri

 I am working on a custom board based on STM32MP267FAK3 and facing issues while flashing eMMC directly using STM32CubeProgrammer.Hardware DetailsSoC: STM32MP267FAK3DDR: DDR3L (part no: MT41K512M16VRP-107 )eMMC: Custom eMMC MX52LM08A11XVW SD Card: Not populated / no SD card provision on boardSoftware Changes DoneI have already made board-specific changes in:TF-A (DDR + PMIC configuration generated using CubeMX tool)OP-TEEU-BootLinux kernelFlashing MethodFlashing eMMC directly using STM32CubeProgrammerInterface: USB (DFU)Using a TSV file generated from the build system (same method as reference BSP)TSV File Problem DescriptionWhen flashing the eMMC, I consistently get a timeout error in STM32CubeProgrammer. My questions are:1. What might be the reason for this error?2. What are the possible solutions I can adopt to resolve this issue?3. Is there any other way to directly flash eMMC without SD card and without using STM32CubeProgrammer?

Hi Team,Does STM32MP257F-DK supports OpenSTDroidIf supports where can i find the starter package for this Discovery board.

Hi everyone,we applied the ST FWU reference solution on our own platform based on the STM32MP157F.The solution was taken and adapted from the ST Yocto layer meta-st-ota (https://github.com/PRG-MPU-CUST/meta-st-ota).In our setup rootfs must become read-only because of dm-verity application on rootfs requested by secure boot scheme.Currently, making rootfs r/o is not possible because of post-install.sh rauc handler, which writes to the rootfs.The problem, that after an update bundle installation, rauc calls the post-install.sh. This script edits MOUNT_PARTITIONS_LIST in the mount-partitions.sh script in rootfs of the next slot to mount correct `-a` or `-b` bootfs or vendorfs after the reset.The solution that we think about, is to remove rootfs changing step from post-install.sh and to make mount-partitions.sh slot aware.  Instead of mounting from MOUNT_PARTITIONS_LIST variable as-is, mount-partitions.sh should read the current slot from /

Hi, I'm trying to understand the firmware / software stack update and I'm quite confused with one thing.I'm quite familiar with the PSA firmware update, metadata, TF-A integration and so on, I've got an access to meta-st-ota.From what I understand, once you find the active boot index in TF-A, the TF-A writes a boot index into backup registers so that it can be propagated to the next stages. But how do you use this index in the next stage (u-boot) actually? I see that indeed it is used in fwu_plat_get_bootidx function which is only available only when CONFIG_FWU_MULTI_BANK is enabled, but it's not used in e.g. rauc boot method. So that why I'm confused. I would rather expect sth like this:- assume active index is set to 0 in metadata- BL2 loads metadata- BL2 lodas boot idx = 0- BL2 sets boot_idx just before it loads BL33- BL2 loads firmware from fip-a- u-boot checks fwu_plat_get_bootidx - u-boot based on boot_idx selects boot-a and root-a (if. boot_idx = 1, u-boot selects

I just need to confirm something. I read in the RM Document that STM32MP157 does not support ODT for LPDDR3 SDRAM but it does have a DDR Controller and PHY which supports LPDDR3. I just wanted to know if I can freeze LPDDR3 for my case? I suppose not giving ODT simply means that I need to provide termination on the PCB itself right? Can someone please throw some more light on this? It would be good to have some reference as well.

Hello,ST has released the STM32MP1 and the newer STM32MP2 series of MPU products. I would like to know what the roadmap looks like after the STM32MP2.Is there any information available about the next-generation STM32 MPU family (e.g., a potential STM32MP3 or a new architecture)?Any official hints or timelines would be greatly appreciated.Thank you.

How can we read GPS data in STM32MP135F-DK