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I'm checking the output of internal opamp in the STM32U083C-DK.In both PGA and Follower modes, I found that the opamp output voltage was lower than the actual input signal. Follower mode/before calibration(Factory trim/0xe13): - Input signal: 0.2502V -> Output signal: 0.2488V PGA mode(Gain: x8)/before calibration: - Input signal: 0.1010V -> Output signal: 0.7942V So, I used the opamp's internal calibration function. Follower mode/after calibration(User trim/0x1f12): - Input signal: 0.2502V -> Output signal: 0.2350V PGA mode(Gain: x8)/after calibration(User trim/0x1f12): - Input signal: 0.1010V -> Output signal: 0.6852V However, the opamp output signal level was further reduced, indicating that something was wrong.Before calibration, the opamp's factory trim code was 0xe13, but after calibration, the user trim code was set to 0x1f12. It appeared that the P terminal calibration value was set to the max (0x1f). (As an additional condition, I opened SB12 on the STM32U083C-DK bo

Hello, I have an STLINK-V3MINIE that I've connected to a B-WB1M-WPAN1 board with a 10 lead cable. I'm trying to flash firmware/my code onto the board, but am running into some errors.First, I tried uploading my code using STM32CubeIDE, but am hitting a "No ST-LINK detected! Please connect ST-LINK and restart the debug session". Sometimes there is also a GDB server error. Then, I tried connecting and flashing firmware using STM32CubeProgrammer. When I first refresh, the ST LINK is detected and I tried updating it through the "Firmware upgrade" button. In the STLinkUpgrade tool (v3.16.8), I get an "Upgrade canceled, corrupted firmware data", then "Upgrade successful" (sometimes I see "Failure exiting upgrade mode (Error 33)" instead of success). When I refresh the device list and open in update mode again, the version of the ST LINK hadn't successfully updated or changed. When I try connecting through CubeProgrammer, the connection fails and I see "UR connection mode is de

In my custom FSBL on an STM32MP135AAE3, everything runs great except anytime I try to modify one of the GIC flags it pretty much ignores me completely (when I read it back, my changed bits aren't changed).  I'm guessing this is some kind of trust zone or secure state or similar situation.BTW, when I run my FSBL by setting the chip to serial boot and uploading it that way, it runs great, so I know the code is solid.What do I need to change so my FSBL has full privileges?  Is there a document that talks about this?

Hi everyone,I'm trying to interface a DVP camera (like OV5640) with the STM32F469I-DISC0 board using the DCMI peripheral in 8-bit parallel mode.What I have:- The camera is configured and outputs data correctly via I2C.- I'm using bare-metal code (no HAL or CubeMX), and SDRAM + USART debug are working.- DCMI pins are being mapped as per the STM32F469 reference manual.- I verified that I can access and remap the following DCMI pins:- D0 – available- D1 – available- D2 – available- D3 – available- D4 – not available(e.g., PE5)- D5 – available - D6 – available- D7 – available- HSYNC, VSYNC, PCLK – availableProblem:- DCMI_D4 is not brought out on any connector** on the DISC0 board. It's internally routed to LCD or unused.- I checked the board schematic and there’s no easy way to solder to it either.My questions:1. Can DCMI work with 7-bit data (skipping D4)? Will DCMI capture still be valid if D4 always reads 0?2. Is there any known workaround for the missing D4 line (e.g., using

Hi!I wonder how I can bypass"Locking RIF conf for peripheral" inside CubeMX.In this case, op-tee is locking peripheral 34, which is the USART6 console output. Hence, that's the last message.I need to unlock peripheral 34. How can I do that?  F/TC:0 0 probe_driver_node:543 Probing stm32-exti on node interrupt-controller@46230000 D/TC:0 0 stm32_exti_rif_parse_dt:423 No global lock on RIF configuration D/TC:0 0 probe_driver_node:556 element: stm32-exti on node interrupt-controller@46230000 deferred 1 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32_gpio-pinctrl on node pinctrl-z@46200000 D/TC:0 0 probe_driver_node:556 element: stm32_gpio-pinctrl on node pinctrl-z@46200000 deferred 1 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32-tamp on node tamp@46010000 D/TC:0 0 probe_driver_node:556 element: stm32-tamp on node tamp@46010000 deferred 1 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32-rtc on node rtc@46000000 D/TC:0 0 probe_driver_node:556 element: stm32

Hello! I have STM32N6570-DK and i would like to disable or make Trust Zone transparent to me and develop the project without safety like your products with cortex M3,M4 and M7 cores with all resources available. I can find some video content on disabling Trust Zone on STM32L5 and STM32U5 but not for STM32N6. STM32CubeIDE offers me a Secure or Secure-Non Secure project generation. Any tips ? Thank you 

Embedded ST-Link via CN1 USB is working fine. I followed the direction as below when external ST-Link v2 was tried on STM32L552ZET6Q Nucleo-144. The error message "No Target" was displayed on STM32CubeIDE with external ST-Link. Could you provide me with any advice?    

Hello everyone,I am working on a custom board based on the STM32U575RGT6 (1MB Flash). I am encountering a hard fault (SecureFault) during the initialization of the Non-Secure application after integrating the SBSFU.Context:Hardware: Custom board with STM32U575RGT6.Initial Project: A working application using TrustZone active + FreeRTOS (generated via CubeMX). The Option Bytes were set to a default 50/50 split (Secure/Non-Secure).Goal: Implement a Secure Boot / Firmware Update mechanism.What I did:I used the ST example for B-U585I-IOT02A as a reference.I integrated SBSFU_Boot and SBSFU_Loader into my project folder.I adapted the linker scripts (.ld), postbuild.sh, and flash_layout.h to match the 1MB Flash size of the U575RGT6 (vs 2MB on the B-U585I).In my original application, I replaced the .ld files and startup_xx.s files with those provided in the SBSFU_Appli example.Configur

Custom board. STM32U5G9. I am running Zephyr and trying to use PB8 and PB9 for the FDCAN peripheral. In loopback mode, it does not get any errors but in normal mode it does. The odd thing is that if I change the pins in the dts file to PA11 and PA12, it works fine.  I am guessing that it is a timing/clock issue or something but I have been arguing with this for two days and I am out of ideas. The device tree entry is: &fdcan1 { // pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>; pinctrl-names = "default"; bus-speed = <250000>; bus-speed-data = <250000>; status = "okay"; can-transceiver { max-bitrate = <250000>; }; }; If I uncomment the first pinctrl (pb8 & pb9) I see no output on the TX GPIO pin (PB9). If it is configured as shown, I do see packets on PA12.   Thanks!

Hello,A question on STM32CubeMX v6.16.1, when  I select OpenAMP in Middleware and Software Packs, I can see configuration options, like COMMUNICATION_MODE, SHM_START_ADDRESS, SHM_SIZE etc, but they are all greyed out and not allowing me to change anything.Is there a way to change these options in STM32CubeMX GUI? (I'm aware that the code generated by CubeMX is cutrrently broken so CubeIDE cannot build this code, and I hope for the fix in the next CubeMX version). Another question - the code in CM33/ folder that is generated by CubeMX, can it be built by the Yocto bitbake, like it does for CA35/ folder?Thanks! Regards,Sergei

Does ST maintain any automated tests for ST development boards and Zephyr?  If so, where may I find more details about the hardware used and test coverage?

This release introduces the latest version of RTEdbg, a high-performance toolkit engineered for real-time embedded system analysis and debugging. The latest update streamlines event visualization via VCD viewers and introduces FreeRTOS trace integration, alongside several core enhancements.Unlike traditional logging and tracing solutions (such as Tracealyzer or SystemView), RTEdbg provides deep runtime insights with a minimal footprint. Its logging functions are significantly faster than commercial alternatives and consume substantially less stack space, making it the ideal choice for both resource-constrained devices and complex, large-scale RTOS-based systems.Relying solely on classical debuggers often feels like "flying blind" when managing intricate timing and RTOS scheduling. RTEdbg bridges this gap by providing:VCD-based visualization for synchronized event and data tracking.RTOS trace support for better scheduling visibility.Enhanced trace macros allowing you to log any data typ

I have been looking at the CRA Q&A and was wondering what you you are meaning with the reporting of security incidents 2026-12-11. Do you mean the reporting according to article 14 that enters into force 2026-09-11?

Not sure that I have the latest version of the HAL but I used two ip address for the ETH MAC and tried to enable both in the L3 filter.But I could not get any data to the second interface. with the filter turned on-Looking more closely on the HAL_ETHEx_SetL3FilterConfig I found what can only be a copy paste mistake.Writing the destination address for IPv4 was mede to the MACL3A0R1R register instead of the expected: MACL3A1R1RMight be fixed in newer version but using two IP-address perhaps is a bit unusual.  

Hello,I'm trying to run a simple validation or application on the NUCLEO‑N657X0 but I can't seem to get past build errors. I don't know if it's the setup in CubeMX or what. Thanks   

Hello, I need to have D-Cache enabled to improve performance of FMC external SDRAM (it's >3x slower without D-Cache enabled). I also want to use I2S for audio. But with D-Cache enabled, I don't get any data from ADC. What can I do to use I2S with D-Cache enabled?

 Hi,I am compiling a MiniFASNet-based liveness ONNX model for STM32N6 using ST Edge AI Core v2.2.0.The model behaves correctly in Python, but when deployed on STM32N6 the performance degrades noticeably.What is confusing is the following:Original ONNX model → good results in PythonST-generated optimized model (*_OE_3_3_0.onnx) → also good results in Python (not compared to original model)Same compiled model running on STM32N6 → significantly worse liveness performanceModel & Compilation DetailsCommand used:./stedgeai generate \ --model best_model_quantized_calib.onnx \ --target stm32n6 \ --input-data-type float32 \ --output-data-type float32 \ --inputs-ch-position chlast \ --no-onnx-optimizer \ --verbosity 3Compilation summary (excerpt):Input: f32 (1x128x128x3)Output: f32 (1x2)Model format: ss/sa per tensor119 epochs (2 software: QuantizeLinear, DequantizeLinear)Native float enabledActivations allocated in NPU RAM regions(Full log pasted below)What Has Been VerifiedPreprocessi

Hello ST Community,I am working on my final year project: an autonomous "Multimodal Medical Assistant Robot" based on the NUCLEO-H723ZG (Cortex-M7, 550MHz). I would like to have your expert opinion on the feasibility and technical architecture.Key Features:100% Offline AI (Edge AI):Audio: Keyword Spotting (7 commands) using INMP441 (I2S) and CMSIS-DSP (MFCC).Vision: Fall detection using OV2640 (DCMI) and a light MobileNet model.Software Stack: X-CUBE-AI, TensorFlow Lite Micro, FatFS.Innovation (Dynamic Loading): We plan to load the AI models (.tflite) and voice responses (.wav) dynamically from a USB Flash Drive (USB Host MSC) into RAM at boot time.Specific Questions:Is the NUCLEO-H723ZG powerful enough to run both Audio and Vision inference concurrently while managing motor control (PWM) and USB Host?Regarding the USB Host / RAM loading: Does X-CUBE-AI support "relocatable weights" loaded into RAM from an external storage device via FatFS? Any specif

Hi.  I have a newly purchased NUCLEO-U575ZI-Q.  I followed the instructions here to install the toolchain on Windows 11:https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html#documentationhttps://wiki.st.com/stm32mcu/wiki/STM32StepByStep:Step1_Tools_installationAfter one unsuccessful attempt where I chose my own installation folders, I uninstalled everything and took the defaults.What a mess!  The default installation folders are spread between AppData, Program Files, and C:\ST.  But OK, if that's what it takes.Unfortunately, I got to step 5 and found that the instructions diverge from reality.They never said to click Finish to complete the Import Projects dialog.  And there is no way to select the project they mention from it.  But if I click Finish, then a tiny icon appears on the upper left.  If I click it, then there is a Project Explorer window.The next step is:My IDE has no Debug icon (the the little yellow blob on its lower left).  Bu

Hello,The latest version of X-CUBE-AI is 10.2.0, which comes with ST Edge AI Core v2.2.0.The latest Edge AI Core version is v3.0.0.The STM32 model zoo release 4.0 adds support for ST Edge AI Core v3.0.0.The STM32 model zoo release 3.2 adds support for ST Edge AI Core v2.2.0.Some of the models from the model zoo release 4.0 fail to generate code with the latest X-CUBE-AI with errors such as "Your model ir_version is higher than the checker's".What are the intended tools to build the models from the modelzoo 4.0 release for the STM32N6, or is only release 3.2 supported?Thanks!

Continuation of this thread. Hello,  I've wired SDRAM (AS4C4M16SA-5TCN)  with STM32H730ZBT. Connection works, I can read/write data, but every other byte.  Let's start with array declaration: uint8_t *externalRAM = (uint8_t*)0xC0000000; /* USER CODE END PV */ Then I'm trying to write some bytes to this array, ie: externalRAM[0] = 0xAA; externalRAM[1] = 0xAA; externalRAM[2] = 0xAA; externalRAM[3] = 0xAA;   And to read it: uint8_t test[4]; test[0] = externalRAM[0]; test[1] = externalRAM[1]; test[2] = externalRAM[2]; test[3] = externalRAM[3]; And this is the result: Sometimes test[1] has 0xAA too, but mostly it's 0. I've tried to lower FMC frequency or change memory timings. What does this look like?

Hello,I am experimenting with X-Cube-AI (v10.2.0) in STM32CubeMX(v6.16.1). I noted that the version of the ST Edge AI Core in this case is v2.2.0. Moreover, this makes that the Embedded Interface is the legacy one, instead of the the newest ST-AI. I wonder if there are plans to update X-Cube-AI so it uses the latest version of ST Edge AI (v3.0.0), and uses the latest the ST-AI interface.Thanks.

In an effort to track down an unrelated problem, I switched back to using my H7 DISCO board and the HSEM_CoreSync sample application. If I debug only the CM7 code, or only the CM4 code, I can step through any/all lines. However, if I try to multi-core debug, single stepping on the CM7 says it is performing a step:(before hitting F5)(after hitting F5)but it really doesn't. As you can see by the left red circle, it claims it is performing a step. In reality it did not step into MPU_Config, it actually performed a continue and is in the Error_Handler call shown in the right hand red circle.Even if I set breakpoints in MPU_Config, hitting any step/continue button will cause it to skip the breakpoint(s) and end up in the Error_Handler. Pausing the CM7 shows the stack as calling that instance of the Error_Handler, and the Fault Analyzer always shows no faults.The compiler options are all set to maximum (-g3), so this shouldn't be a problem of trying to debug optimized code.Does anyone have a

Dear ST Community,We are working with the STM32MP257F-EV1 evaluation board and using the Yocto Distribution Package for our software stack.Our intended boot sequence is:Boot starts from the Cortex-M33 core.The M33 firmware is responsible for triggering the boot of the Cortex-A35 core.We would like to confirm:Is this boot flow supported on the STM32MP25x platform?If yes, could you please share the recommended procedure or reference steps to implement this?Any guidance or official documentation links would be greatly appreciated.Thanks and Regards,Ishan

I get this type of error when I'm trying to setup a project with Nucleo-H563ZI and GCC here:I also get information that gdb is not running, while I've installed everything in the same way as I did on my previos laptop im my work. I've even changed system env for not checking tls or sha256 in stm but it still ain't working. Don't know what can I do.