How to use clock configuration in STM32CubeMX2 for STM32C5

B.Montanari · ‎2026-03-16

Summary

This article explains how to understand and configure the STM32C5 clock system in STM32CubeMX2 by directly relating the graphical STM32C5 Clock view to the formal description in RM0522. It shows how the Reset and Clock Control (RCC) manages both reset and clock distribution. Additionally, how the device always starts from a known default state (SYSCLK from HSIDIV3 at 48 MHz). Finally, how SYSCLK is derived from HSI, PSI, or HSE and then propagated through AHB/APB prescalers to the core, buses, timers, and peripherals.

A hands‑on example of NUCLEO‑C562RE illustrates how changing clock sources and prescalers in STM32CubeMX2 translates into specific RCC register configurations in the generated initialization code, following the behavior described in RM0522.

Summary
Introduction
Prerequisites
1. RCC and system reset context
2. System clock sources and the clock tree
3. High-speed clock sources: HSE, HSI, and PSI
3.1 HSE: external high-speed clock
3.2 HSI: High‑speed internal oscillator
3.3 PSI: Precise‑Speed internal oscillator
4. Dividers and kernel clocks: HSIDIV3, PSIDIV3, HSIK, PSIK
5. Low‑speed clocks: LSE, LSI, LSCO and RTC
6. System clock selection and low‑power behavior
7. Clock outputs: MCO1, MCO2 and LSCO
8. CRS and HSI trimming in practice
9. Hands-on
9.1 STM32CubeMX2 project creation and basic setup
9.2 Clock tab use case
Conclusion
Related links

Introduction

On STM32C5, the Reset and Clock Control (RCC) block is at the heart of the device:

It generates and distributes clocks to the core, buses, and peripherals.
It supervises all reset sources and brings the device back to a defined state.

The clock configuration selected directly shapes:

CPU performance.
Peripheral timing (timers, communication interfaces, analog IPs).
Power consumption in low‑power modes.
Frequency accuracy for interfaces such as USART, USB, FDCAN, and watchdogs.

The STM32C5 family provides a structured clock architecture built around a few primary sources:

HSI: internal high‑speed oscillator.
PSI: precise‑speed internal oscillator.
HSE: external high‑speed oscillator (crystal or clock input).
LSI and LSE: low‑speed internal and external oscillators.

These complement:

Dedicated dividers: HSIK, PSIK, HSIDIV3, PSIDIV3.
Per‑peripheral kernel clock multiplexers.
Dedicated clock outputs: MCO, LSCO.

The clock chapter of RM0522 defines how these elements interconnect, while the STM32C5 clock view in STM32CubeMX2 presents the same structure graphically.

Prerequisites

Install the following tools:

STM32CubeMX2
The latest STM32C5 HAL2 driver
STM32CubeIDE extension for Visual Studio Code

The hardware used in this tutorial is the NUCLEO-C562RE board.

1. RCC and system reset context

RM0522 (RCC chapter) states that RCC is responsible for managing resets and generating clocks for the buses and peripherals. It distinguishes three reset classes:

Power reset (POR/PDR, Standby exit), which resets almost all registers except those in the RTC domain.
System reset, triggered by NRST, watchdogs, software, low‑power security, or POR. This resets the core domain while preserving the RTC domain and the reset source flags in RCC_RSR.
RTC domain reset, controlled by RTCDRST in RCC_RTCCR or by a fresh power‑on of VDD, which specifically affects LSE, RTC, backup registers, and RCC_RTCCR.

From the clock configuration point of view, this matters because after a system reset or when leaving Standby, the device always starts from the same known clock state: HSIDIV3 at 48 MHz is selected as SYSCLK, and many RCC registers return to their reset values. The reset flags in RCC_RSR (for example SFTRSTF, PORRSTF, PINRSTF) allow the application to determine the reset cause. STM32CubeMX2 assumes this reset state when generating STM32C5 clock configuration code.

2. System clock sources and the clock tree

The RM0522 chapter 9.4 describes the main STM32C5 clock tree. There are four possible SYSCLK sources:

HSIS: high‑speed internal clock at 144 Mhz (HSI direct path).
HSIDIV3: HSI divided by 3, at 48 Mhz.
PSIS: precise‑speed internal clock derived from PSI (up to 160 MHz, but SYSCLK is limited to 144 MHz).
HSE: external high‑speed oscillator (crystal or clock) in the range defined by RM0522 and the datasheet.

After reset or standby exit, HSIDIV3 at 48 MHz is automatically selected as SYSCLK. When you later switch SYSCLK via RCC_CFGR1.SW[1:0], the switch occurs only after the target clock’s ready flag (such as HSISRDY in RCC_CR1) is set. The active SYSCLK source is indicated by RCC_CFGR1.SWS[1:0].

In RM0522 Figure 24, SYSCLK (labeled sys_ck) feeds the AHB clock tree. The AHB prescaler HPRE in RCC_CFGR2 divides SYSCLK to produce rcc_hclk. This drives the AHB bus, core, memories, DMA, and the Cortex®‑M33 FCLK, as well as all “standard” timers whose kernel clocks equal HCLK. rcc_hclk is also the base for APB clocks via the APB1/2/3 prescalers PPRE1, PPRE2, and PPRE3 in RCC_CFGR2. APB prescalers allow you to run APB buses slower than HCLK, and the *_DIS bits such as APB1DIS and AHB1DIS let you gate entire bus domains to save power.

In STM32CubeMX2, this mapping appears at the top of the STM32C5 clock view. SYSCLK selection, HCLK (AHB prescaler), and PCLK1/2/3 (APB1/2/3 prescalers) are shown with the resulting bus frequencies computed in real time.

3. High-speed clock sources: HSE, HSI, and PSI

3.1 HSE: external high-speed clock

HSE is driven by a crystal/ceramic resonator or by an external clock source in bypass mode. In crystal mode, you connect a resonator and its load capacitors to OSC_IN and OSC_OUT, then enable HSE by setting HSEON in RCC_CR1 with HSEBYP = 0. In bypass mode, you provide a digital or low‑swing clock on OSC_IN, configure HSEBYP and HSEEXT, then enable HSEON.

The HSERDY flag indicates when HSE is stable. As long as HSE is used as SYSCLK or as the PSI reference (with PSI enabled), HSEON cannot be cleared. HSE is automatically disabled in Stop or Standby modes unless it is indirectly kept via PSI under specific low‑power conditions (see PSIKERON). HSE can be routed to MCO1 or MCO2 for external measurement.

In STM32CubeMX2, you simply enable HSE in the Clock Configuration, select “Crystal/Ceramic” or “Bypass”, and the tool configures HSEON, HSEBYP, HSEEXT and validates the frequency against the datasheet.

3.2 HSI: High‑speed internal oscillator

HSI is the default high‑speed clock source for STM32C5. It is an internal 144 MHz oscillator that can drive SYSCLK and many peripheral clocks. RM0522 chapter 9.4.2 defines three distinct outputs derived from HSI:

HSIS: the undivided 144 MHz path.
HSIDIV3: HSI divided by 3, nominally 48 MHz.
HSIK: HSI divided by a programmable factor between 1 and 8, including fractional values such as 1.5, 2/5, …, 7.5 configured via HSIKDIV[3:0] in RCC_CR2.

The bits HSISON, HSIDIV3ON, and HSIKON allow each path to be enabled independently, and the flags HSISRDY, HSIDIV3RDY, and HSIKRDY indicate when each output is stable. HSIDIV3 is selected as SYSCLK after reset and Standby. Hardware can automatically turn HSIDIV3 on (by setting HSIDIV3ON) if HSE fails while used as SYSCLK (directly or through PSI), or when exiting Stop mode with STOPWUCK = 0. If STOPWUCK = 1, HSIS is automatically enabled on Stop exit.

RM0522 emphasizes that HSI is less accurate than a crystal, even after calibration, but starts faster and reduces BOM cost. It can be kept running in Stop 0 through HSIKERON, so HSIS, HSIDIV3, and HSIK are immediately available on wake‑up, which is particularly important if they serve as kernel clocks for communication peripherals.

Calibration is performed via the TRIM[6:0] bits in the CRS control register CRS_CR. A factory value is loaded at power‑on, and the application can adjust it for voltage and temperature variations. The CRS block can automate trimming using a reference such as HSE (via hse_1M_ck), LSE, USB SOF, or an external synchronization signal.

In STM32CubeMX2, enabling HSI and selecting it as SYSCLK (HSIS) or as the source for USB/HSIK is done by clicking the corresponding nodes in the STM32C5 clock tree. CRS configuration for HSI auto‑trim is accessible in the CRS peripheral configuration panel.

3.3 PSI: Precise‑Speed internal oscillator

PSI is a PLL‑like internal oscillator that generates precise high‑speed clocks at 100, 144 or 160 MHz depending on PSIFREQ[1:0] in RCC_CR2. It operates only when supplied with an appropriate reference clock of 32.768 KHz or about 8.33 MHz, selected through PSIREFSRC[1:0] and PSIREF[2:0].

RM0522 Table 63 lists valid combinations of reference source and frequency. The reference can be LSE at the usual 32.768 KHz, HSE at various supported frequencies or HSI divided by 18. When LSE is used as the reference, a small intrinsic error on the PSI output (for example 100.016 MHz or 144.0151 MHz), due to the fractional ratio.

PSI also provides three outputs:

PSIS: main high‑frequency output at 100, 144 or 160 MHz.
PSIDIV3: PSI divided by 3, used notably for USB and RNG.
PSIK: PSI divided by a programmable factor between 1 and 8, via PSIKDIV[3:0] in RCC_CR2, mirroring the HSIK behavior.

The bits PSISON, PSIDIV3ON, and PSIKON in RCC_CR1 control these outputs, and PSISRDY, PSIDIV3RDY, and PSIKRDY indicate that each is ready. PSIS can be selected as SYSCLK, but RM0522 states clearly that SYSCLK must not exceed 144 MHz even if PSI can generate 160 MHz, and the 160 MHz must not be propagated to peripheral kernel clocks.

Like HSI, PSI can be kept active in Stop 0 by setting PSIKERON, along with its reference clock, allowing PSIS, PSIDIV3, or PSIK to restart quickly on wake‑up.

In STM32CubeMX2, you configure PSI by choosing the reference source (HSE, LSE, or HSI/18), selecting the PSI target frequency, and enabling PSIS, PSIDIV3, and/or PSIK. The tool checks that your selection is valid and within STM32C5 electrical limits.

4. Dividers and kernel clocks: HSIDIV3, PSIDIV3, HSIK, PSIK

HSIDIV3 is derived from HSI by division 3, providing a nominal 48 MHz clock. It is used by USBFS and RNG and serves as a safe fallback SYSCLK if HSE fails. When CRS is enabled, HSIDIV3 becomes the basis for crystal‑less USB: CRS continuously adjusts the HSI trim based on a reference (USB SOF, LSE, HSE, or an external signal) so that HSIDIV3 meets USB tolerance.

PSIDIV3 plays a similar role but inherits the stability of PSI when locked to HSE or LSE. It also provides a precise 48 MHz domain for USB and RNG when configured properly.

HSIK and PSIK are flexible dividers that generate a wide range of kernel frequencies from HSI or PSI. RM0522 Table 64 shows the resulting frequencies for different divider values. For example, with PSI at 144 MHz, a PSIK divider of 3 yields 48 MHz, fairly used by USB, if a 1.5 is used, this leads to a 96 MHz, common for FDCAN timebase and so on.

In STM32CubeMX2, the HSIKDIV and PSIKDIV settings are chosen graphically, and the resulting hsik_ck and psik_ck appear as options in the kernel clock multiplexers of multiple peripherals.

5. Low‑speed clocks: LSE, LSI, LSCO and RTC

The low‑speed clock domain involves LSE, LSI, and LSCO, all described in RM0522.

LSE is the 32.768KHz external crystal/ceramic resonator or external clock connected to OSC32_IN and OSC32_OUT. It is controlled by LSEON, LSEBYP, LSEDRV[1:0], and LSEEXT, and its state is indicated by LSERDY. LSE can be protected by a clock security system using LSECSSON and LSECSSD. LSE resides in the RTC domain (via RCC_RTCCR) and is not affected by a system reset.

LSI is an internal RC oscillator running around 32 KHz, controlled by LSION and LSIRDY bits. It can clock the independent watchdog (IWDG) and serve as RTC clock when no external crystal is present. LSI may remain active in Stop and Standby if required by IWDG.

LSCO is a low‑speed clock output that can be driven by either LSI or LSE and routed to a dedicated pin. It is configured with LSCOSEL and LSCOEN in RCC_RTCCR.

The RTC/AWU clock rtc_ck can be sourced from HSE divided by RTCPRE (hse_1M_ck), from LSE, or from LSI. This choice is made via RTCSEL[1:0] in RCC_RTCCR. The selection is write‑once, unless you reset the RTC domain with RTCDRST, which is why RM0522 insists that RTCSEL must be selected carefully and early in system initialization. LSE CSS can be enabled so that a failure on LSE generates an NMI; software must then move the RTC to another clock source.

In STM32CubeMX2, LSE and LSI are shown as separate blocks in the STM32C5 clock tree. You choose the RTC clock source in the RTC configuration panel and may enable LSCO as an external output for measurement and debugging.

6. System clock selection and low‑power behavior

SYSCLK selection is performed through RCC_CFGR1.SW[1:0], which allows you to select HSIS, HSIDIV3, PSIS, or HSE as SYSCLK. The current SYSCLK source is reflected in RCC_CFGR1.SWS[1:0]. RM0522 clearly states that SYSCLK must not exceed 144 MHz, even though PSI can run at 160 MHz and that this upper limit frequency must not be used as SYSCLK or as a peripheral kernel clock.

In Stop modes, HSI, PSI, and HSE are normally disabled, and system and kernel clocks are stopped. In Stop 0, however, HSIKERON and PSIKERON can keep HSI or PSI running, and HSE may also be active if it is used as PSI reference. The availability of HSIS, HSIDIV3, HSIK, PSIS, PSIDIV3, and PSIK on wake‑up then depends on their respective enable bits (HSISON, HSIDIV3ON, HSIKON, PSISON, PSIDIV3ON, PSIKON).

Upon exit from Stop, the wake‑up SYSCLK source is selected automatically based on STOPWUCK: if STOPWUCK = 0, HSIDIV3 is used; if STOPWUCK = 1, HSIS is used. When leaving Standby, SYSCLK is always HSIDIV3 at 48 MHz, and HSI user trim is lost, which is why any high‑precision configuration based on HSI must re‑initialize CRS and trimming after Standby.

In STM32CubeMX2, STOPWUCK and low‑power behavior are configured in the RCC low‑power options, and the STM32C5 clock view visually indicates which clocks remain active in each Stop mode.

7. Clock outputs: MCO1, MCO2 and LSCO

There are three clock signals that can be outputted, the Microcontroller Clock Outputs (MCO1 and MCO2) and a low‑speed clock output (LSCO).

MCO1 and MCO2 are configured using MCO1SEL, MCO1PRE, MCO2SEL, and MCO2PRE in RCC_CFGR1. Depending on the selected options, they can output SYSCLK, HSE, LSE, LSI, PSIK, HSIK, PSIDIV3, HSIDIV3, HSIS, or PSIS. The output can be prescaled by up to a factor of 15.

The corresponding GPIO pins must be configured in alternate‑function mode, and their maximum speed must not be exceeded. In Stop 0, only clocks that can act as SYSCLK (HSIS, PSIS, HSIDIV3, HSE) remain available on the MCO pins, and only if they are kept active via HSIKERON or PSIKERON.

LSCO is configured via LSCOSEL and LSCOEN in RCC_RTCCR and can output either LSI or LSE. It remains available in Stop modes but not in Standby.

In STM32CubeMX2, MCO1 and MCO2 sources and prescalers are set in the STM32C5 clock view, and the corresponding pins are assigned through the GPIO configuration. LSCO selection is handled in the RTC configuration (RCC_RTCCR).

8. CRS and HSI trimming in practice

The clock recovery system (CRS), described in RM0522 chapter 10, is closely integrated with HSI. RM0522 describes it as an advanced digital controller acting on the fine‑granularity trimmable HSI144 RC oscillator. CRS compares a synchronization signal (USB SOF, HSE_1M, LSE, or an external source) with HSI‑derived timing and automatically adjusts TRIM[6:0] to minimize frequency error. It supports automatic and manual trimming, a 16‑bit error counter, programmable error limits, and events or interrupts such as SYNCOK, SYNCWARN, and ERR.

In a typical STM32C5 USB device project that uses crystal‑less USB, HSI, and HSIDIV3 are enabled. HSIDIV3 is selected as USB CK48 via CK48SEL = 10 (HSIDIV3), and CRS is configured with USB SOF as the synchronization source and appropriate prescaler and polarity. As USB SOF packets arrive, CRS updates the HSI trim automatically so that HSIDIV3 remains within USB tolerance.

STM32CubeMX2 can generate this entire initialization sequence: it enables CRS, HSI, HSIDIV3, selects CK48SEL, and configures the USB peripheral accordingly.

9. Hands-on

9.1 STM32CubeMX2 project creation and basic setup

Follow these steps to configure the CLOCK in your project for the NUCLEO-C562RE board:

Open STM32CubeMX2. On the Home page, click the MCU square to create a new project.

In the search field under MCU name, enter STM32C562RE and select your board. Click Continue.

Enter your project name and location. Click [Automatically Download, Install & Create Project] to finish project creation.
Launch the project.

9.2 Clock tab use case

The default view shows the HSI being used as the entry point of the PSI.

Notice that the LSE and HSE are not available at this point in time, as it is necessary to enable them via the Peripherals/System/RCC.

Each one of those options, when changed, cause your generated code to change. To see it in the code before generation, the [Code Preview] can be used.

Let’s change the clock source to use the 24 MHz HSE, available on the NUCLEO board as well as the 32.768 kHz for the LSE.

In the "Clock" tab, change the PSI entry point and HSE value.

Now, go back to the RCC peripheral tab and use the code preview to inspect the change:

Conclusion

The STM32C5 clock architecture offers a precise, flexible, and highly configurable timing foundation for embedded applications. By combining a small set of primary sources (HSI, PSI, HSE, LSE, LSI) with dedicated dividers (HSIDIV3, PSIDIV3, HSIK, PSIK) and per‑peripheral kernel clocks. It allows you to tune performance, accuracy, and power consumption at subsystem level.

When you interpret the clock system through the RCC chapter of RM0522 and configure it via the STM32C5 clock tab in STM32CubeMX2, every graphical choice has a well‑defined counterpart in RCC registers and a documented effect on low‑power and reset behavior.

With this mental model, you can confidently choose a SYSCLK strategy. You can distribute clocks to buses and peripherals. You can also enable advanced features, such as crystal-less USB, using HSIDIV3 and CRS. This approach helps you achieve a clock configuration that is powerful and predictable in real projects.