multi-Slave SPI using STM32F4's?
I am trying to implement a star SPI interface, using STM32F4 as a single master, and interfaces with multiple STM32F4 MCU using SW managed NSS.
I have made sure that SSI is cleared when NSS is activated and set when NSS is deactivated so that the SCK on the common line will not shift the data out of the deselected slave. However, I am still having corrupted data received by the master and I think the problem is due to the fact that the MISO pin of deselected slave is not in High Impedance state.
While searching through the forum, I stumbled upon a similar post https://community.st.com/s/question/0D50X00009XkZWvSAN/multislave-spi-using-stm32f7s, in which it is mentioned that the MISO of all slaves should be configured in Alternate Function Open Drain mode instead of Alternate Function Push Pull, in the Reference Manual of STM32F7.
I gave it a try but the Master was then not able to read any data from the selected slave anymore.
My questions are:
- Was the recommendation of making MISO AF OD on the slaves only applicable to STM32F7?
- Is it true that the MISO pin is not automatically changed to Hi-Z state when NSS is not activated (when the frame protocol is not TI Mode), or am I doing something wrong?
End note: I did try to toggle the MISO pins between input mode when deselected and AF_PP when selected, as a workaround and it does work. Just wish to have the fastest approach. Using HW managed NSS did not seem to work.
Thanks in advance for answering
