STM32MPUs bring-up troubleshooting guide
If It is the first time the boot chain is starting but fails, please see the common pitfall below to get help
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This article applies for STM32MP1 and STM32MP2 series.
1. Common pitfall
Issue: Only PANIC lines appear in the console.
- Check the HSE source configuration issue
ROM CODE makes auto detection of the HSE configuration (crystal or oscillator).
If TF-A reconfigures wrongly, it can stop after reconfiguration.
See https://wiki.st.com/stm32mpu/wiki/Clock_device_tree_configuration_-_Bootloader_specific
- Check configuration I2Cbus connection to STPMIC
I2C bus for pmic is done at an early phase and raises a panic when the bus fails to be enabled.
In OpenSTLinux by default, TF-A expects STPMIC on I2C4 on STM32MP157-DK or I2C7 STM32MP257-DK. If this is not the case on your design, device tree and TF-A code have to be modified.
See https://wiki.st.com/stm32mpu/wiki/PMIC_hardware_components#TF-A
2. What to do if the ROM Code does not answer to STM32CubeProgrammer
Symptom: No MP1 USB profile returned upon host PC at enumeration.
Check the serial boot interface connection pins on the printed circuit board (PCB) for UART or USB OTG.
Check the internal state of the boot ROM with the PA13 pin or, for the STM32MP2 series, with the PH4 pin:
- PA13 is an open-drain signal that toggles slowly, at approximately 5 Hz, when the boot ROM waits for a USB or serial connection.
- PA13 is an open-drain signal that toggles quickly, at approximately 5 kHz, during engineering boot.
- PA13 does not toggle and remains high-Z if the first-stage bootloader (FSBL) is detected successfully from flash memory.
- PA13 does not toggle if the STM32MP1 remains in reset, whatever the cause: NRST low, NRST_CORE low, VDD too low, or VDDCORE too low.
Check that the STM32MP1 is not held in reset.
Check the voltage on VDD_CORE, VDD, and VDDCPU for STM32MP13 or STM32MP2.
Check that NRST and NRST_CORE are high.
Check that PWR_ON is high.
3. Wrong TF-A binary on serial
Since version 2.x, there are two TF-A binaries:
- One binary boots from a serial link and uses the USB/UART stack to interact with STM32CubeProgrammer.
- One binary boots from a flash device. It does not contain serial stacks such as USB and UART to save space.
Since version 3.x, one TF-A binary is compiled for a given boot device, such as USB, UART, SD card, or eMMC.
Load TF-A into SYSRAM with STM32CubeProgrammer and boot ROM code from USB:
STM32_Programmer.sh -c port=usb1 -w ../build/trusted/tf-a-stm32mp157c-displayboard-mx-trusted.stm32 0x01 --start 0x01
NOTICE: CPU: STM32MP157CAB Rev.B
NOTICE: Model: Display Board
WARNING: VDD unknown
INFO: Reset reason (0x4):
INFO: Pad Reset from NRST
INFO: Using USB
INFO: Instance 2
INFO: Boot used partition fsbl1
ERROR: Boot interface 6 not supported
PANIC at PC : 0x2ffd5a99
Exception mode=0x00000016 at: 0x2ffd5a99
In 3.x TF-A code, boot_interface_selected = 6 means that the TF-A compilation flag STM32MP_USB_PROGRAMMER is not defined. Here, TF-A is compiled for another boot device than USB.
4. Kernel hangs
Symptoms: Kernel traces stop, and nothing happens.
Check that no pinctrl definitions for RCC MCO_1, MCO_2, or output GPIO are present in the RCC node of the device tree.
5. Kernel console commands and traces
Symptoms: No command can be entered in the console, but the traces are correct.
To switch the console UART node to interrupt mode, delete the dmas and dma-names properties:
6. SD card voltage error in U-Boot
"Loading Environment from EXT4... Card did not respond to voltage select!"
Instead of: "Loading Environment from EXT4... OK"
This error occurs when the SD card never responds to U-Boot commands.
TF-A boots correctly from the SD card, but U-Boot cannot access it. The issue might occur when the sdmmc1 node contains incorrect properties in the U-Boot device tree source (DTS) file, such as power-supply or level-shifter properties.
Check whether the sdmmc1 node matches the printed circuit board (PCB) design, with or without a level shifter:
- STM32MP1 SDMMC1 is directly connected to the SD card socket, as in the STM32MP157F-DK2 case. See the DK2 U-Boot
sdmmc1device node as a reference. - STM32MP1 SDMMC1 is connected to the SD card socket through an SDMMC level shifter, as in the STM32MP157F-EV1 case. See the EV1 U-Boot
sdmmc1device node as a reference.
https://wiki.st.com/stm32mpu/wiki/SDMMC_device_tree_configuration#DT_configuration_examples
7. DDR intensive noise burst or stress tests: what to check?
Check the following typical pitfalls:
- Check whether the track length constraints are fulfilled in the layout. Refer to AN5122 for the length of DDR signal lanes.
- A 24 MHz oscillator, not a crystal or resonator, is strongly recommended if the design uses LTDC outputs. See the errata sheet.
- Check for supply noise on VDDQ_DDR and DDR_VREF lines.
- When DDR tests fail, analyze the results to determine whether the failure occurs on specific data or address lines.
- A procedure is available in AN5168, section 8.4, "Test flow," and section 3.4, "PHY timings."
- DDR settings in STM32CubeMX DDR parameters are described in AN5168.
- Impedance on DQ/DQS byte lines can be modified. Refer to AN5168, section 5, and section 6 for timing relaxation details and for information about how to change these settings. For STM32MP2, refer to AN5723.
- If the PCB layout is based on ST PCB layout examples or ST boards, DRAM operation should be successful. Signal integrity tests have passed on the connection between the DRAM and the microprocessor unit (MPU) for STM32MP1 or STM32MP2.
8. Incorrect ECC parameters in the U-Boot device tree cause incorrect SLC NAND flashing by STM32CubeProgrammer.
Symptoms:
- ROM code does not start.
- U-Boot detects all NAND partitions.
- STM32CubeProgrammer flashes successfully but displays the error message "Skipping bad block at 0x07f80000."
U-Boot flash service misprograms the NAND because the U-Boot device tree shows properties that are not aligned with the selected NAND datasheet: nand-ecc-strength = <8>; nand-ecc-step-size = <512>;
For more information, see https://wiki.st.com/stm32mpu/wiki/FMC_device_tree_configuration#DT_configuration_of_the_NAND_Flash_controller_-28board_level-29
9. ROM code issue with QUADSPI NAND
Symptom: NAND can be accessed with U-Boot, but ROM code cannot boot from NAND.
- Set OTP#9 according to the NAND datasheet parameters, especially the number of planes.
- Check that the NAND pin connections are compatible with the ROM code serial NAND pins.
- Check the TF-A header.
- Check the configuration of all memory pins: WP#/IO2 and HOLD#/IO3
10. Common SLC NAND bring-up pitfalls
- U-Boot hangs during NAND initialization.
Check that the NWAIT internal pull-up is present in the U-Boot device tree (DT).
- The ROM code does not start.
Check whether the OTPs are virgin.
Check the pinout, and verify that the power domain is on for the NAND supply.
Check whether the NAND is ONFI compatible. Otherwise, use OTP 9 configuration (see the ROM code overview wiki article).
Check whether the NAND is multplane. The ROM code does not support multiplane NAND.
If revision B flash is ONFI compliant with 1-bit ECC, it does not work.
Check the memory datasheet against the U-Boot ECC parameter in the device tree (DT) for FMC ECC algorithm selection. For flash programming, U-Boot does not rely on ONFI.
11. U-Boot: Mac address not set in OTP: Is it blocking? No
U-Boot error:
"Invalid MAC address in OTP 00:00:00:00:00 stm32_smc: Failed to execute svc=82001003 op=1 in secure mode (err = -3)"
This warning indicates that the MAC address is not written in the one-time programmable (OTP) memory of the device.
In this condition, the Linux kernel uses a random MAC address, so this warning is not critical.
U-Boot fails to initialize Ethernet, so the issue affects only U-Boot networking.
To bypass this issue, set the MAC address manually at the U-Boot prompt with the following commands:
- setenv .flags ethaddr
- setenv ethaddr 11:22:33:44:55:66
To continue the boot after setting the MAC address, type run bootcmd.
12. U-Boot hangs during bring-up when U-Boot initializes SLC NAND.
DRAM: 128 MiB
Clocks:
- microprocessor unit (MPU): 650 MHz
- MCU: 208 MHz
- AXI: 266.500 MHz
- PER: 24 MHz
- DDR: 533 MHz
WDT: Started with servicing (32 s timeout)
NAND: Hangs
Check the pin multiplexing, supply, and internal pull-up on NWAIT (see AN5031 for the internal pull-up).