STM32 MPUs

I am struggling with getting a STM32mp25D board flashed, it hangs at BL32 (see output below). It does have one warning "WARNING: Could not enable VRSEL for vddio2", but I don't think that is relevant to the hanging at BL32 (but I could be wrong). I have successfully flashed a STM32mp25F-EV1 board, that works fine. Seeing as the difference between the D and F flavor is that F supports secure boot, I have attempted to tweak OPTEE settings, such as building  OP-TEE OS with configuration CFG_STM32MP_PROFILE=system_services, as suggested here. I have also attempted to set BOOTSCHEME_LABELS = "opteemin" in the boot scheme section of the stm32mp25.conf file. Someone else on the team is also tweaking firewall/security settings, also with no success. I'm not sure exactly what they have attempted on that front, however. I am wondering if someone else has run into this problem/has a solution? I'm also unsure if I'm barking up the wrong tree thinking that the issue lies with OPTEE/f

Hi!I am working on the STM32MP257F-DK board for a robotics project. For this, I want to map some of the GPIO to M33 in order to control the motors while the Linux of the A35 will run the ROS software. From what I understood is follows:I need to customise the device tree to give the permissions of the GPIO to M33 (I initially tried directly flashing with a STM32CubeIDE project and the mpu got reset)I need OpenAMP to communicate between the processors (A35 needs to send calculated moves to M33)How to achieve it I am not sure and I am unable to do it. I went through the STM resources but I am finding it quite confusing.I have installed the Developer-Package, Distribution-Package and Starter-Package as given in following documents:https://wiki.st.com/stm32mpu/wiki/Getting_started/STM32MP2_boards/STM32MP257x-EV1/Develop_on_Arm%C2%AE_Cortex%C2%AE-A35/Install_the_SDK https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package#Installing_the_OpenSTLinux_distribution https://wiki.

Hi,I'm experiencing a fetching error with m4projects-stm32mp1 while building st-image-weston.First i had problem while fetching from:git://github.com/STMicroelectronics/STM32CubeMP1.git;protocol=https;branch=masterSince github doesn't support git: protocol anymore i changed that to https.But i still have fetching errorERROR: m4projects-stm32mp1-1.7.0-r0 do_fetch: Bitbake Fetcher Error: FetchError('Unable to fetch URL from any source.', 'https://github.com/STMicroelectronics/STM32CubeMP1.git;protocol=https;branch=master')I can clone this repo manually but yocto doesn't.Cloning that takes some time (about 2 minutes) but yocto fails quickly. Seems it doesn't even tries to wait fetching to finish.Are there any thoughts how to solve that?

SummaryI'm attempting to add support for a custom STM32MP135-based board (M5Stack CoreMP135) to Yocto using meta-st layers, but the u-boot-stm32mp recipe appears to enforce rigid constraints that prevent using custom defconfigs and device trees. Environment- **Yocto Version**: Kirkstone- **meta-st Version**: OpenSTLinux 5.0 (Kirkstone)- **Target Board**: M5Stack CoreMP135 (STM32MP135DAE7, 512MB RAM)- **U-Boot Version**: v2022.10-stm32mp-r2- **Reference**: M5Stack successfully builds this board with Buildroot using custom defconfig Problem Description What Works in BuildrootM5Stack's Buildroot configuration successfully builds U-Boot for the custom board using:```BR2_TARGET_UBOOT_BOARD_DEFCONFIG="coremp135"BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_ST_PATH)/board/m5stack/coremp135/uboot-dts/*"BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="dtb-y=stm32mp135f-coremp135.dtb DEVICE_TREE=stm32mp135f-coremp135"``` Attempts in Yocto (All Failed) Attempt 1: Using UBOOT_MACHINE Override**Machine config:

Dear all,We have a design where the VCCQ of eMMC is currently 3.3V. We need to move to 1.8V to be able to use a new referenceIs there any risk to break somthing if I use the below DTS on board where eMMC is 3.3V VCCQ. We have pull up to VCCQ on D0 and CMDvqmmc-supply = <&v1v8>; mmc-ddr-1_8v;According to my tests, system is up and running, but I fear this should have an impact on MPU padsIf no risk, this could avoid me to add a DTS overlay according to my hardware board version in case of 3.3V VCCQI add my layout for eMMC for better understanding, see R353 and R356 to switch VCCQThanks in advance for answers and hintsRegardsLaurent  

Hi!I have a STM32MP257F processor. The clock for SDMMC1 is constant at 3.3V. Therefore the U-boot cannot read the SD-card.My question is: What clock need to be active/chosed in the device tree so it u-boot can read the SD-card sdmmc1? Hit any key to stop autoboot: 0 Boot over mmc0! Saving Environment to MMC... stm32_sdmmc2 mmc@48220000: stm32_sdmmc2_getcd called stm32_sdmmc2 mmc@48220000: bus_with = 1, clock = 0 stm32mp25_reset clock-controller@44200000: reset id=69 offset=0x830 bit=0 status=1 stm32mp25_reset clock-controller@44200000: reset id=69 offset=0x830 bit=0 status=0 D/TC:? 0 tee_ta_init_session_with_context:562 Re-open trusted service a8cfe406-d4f5-4a2e-9f8d-a25dc754c099 F/TC:? 0 pta_scmi_invoke_command:404 SCMI command 0x3 ptypes 0x3 F/TC:? 0 pta_scmi_invoke_command:404 SCMI command 0x4 ptypes 0x651 F/TC:? 0 regulator_disable:142 v3v3 D/TC:? 0 tee_ta_close_session:465 csess 0x8212f890 id 1 D/TC:? 0 tee_ta_close_session:484 Destroy session D/TC:? 0 tee_ta_init_session_wi

Hello,I tried to understand what does A35-TD does better than M33-TD flavor and vice versa. But I don't find enough information. The information that confuses me is it says A35-TD Flavor has Hard real time on Arm Cortex-M33. What does it mean operation wise- what capabilities does it have extra compared to M33-TD Flavor? Could someone please help me understand this?  Thanking.with regardsAmit

I'm working on adding a custom STM32MP257 board based on the openstlinux distribution package, and I'm currently using the STM32MP257F-EV1 board. I'm having problems with booting on eMMC with a stm32cubemx-generated device tree. What I've done:* Created a STM32MP257F-EV1 project in CubeMX. I've only changed the project name, no pinning etc (based on instructions from https://wiki.st.com/stm32mpu/wiki/How_to_create_STM32MPU_projects_with_STM32CubeMX#Create_an_STM32MP2_series_project)* Copied the generated output into layers/meta-st/meta-st-stm32mp-addons/mx* Copied stm32mp25-mx.conf to a custom one and edited (perhttps://wiki.st.com/stm32mpu/wiki/How_to_create_your_own_machine)BOOTSCHEME_LABELS += "optee" [...] BOOTDEVICE_LABELS += "sdcard" BOOTDEVICE_LABELS += "emmc" * Built the image usingDISTRO=openstlinux-weston MACHINE=stm32mp257f-simon source layers/meta-st/scripts/envsetup.sh bitbake st-image-westonwhich finishes successfully (CUBEMX_DTB, CUBEMX_PROJECT etc being set in

The project requirement is to use optical ethernet with STM32MP257F. I want to try this interfacing first at STM32MP257F EV1 with some copper to optical Ethernet converter module, but in STM32MP257F EV1, Ethernet pins are not available for interfacing. Kindly suggest some solution for using optical ethernet with STM32MP257F.     Kindly send the solution as early as possible.     Thank you With Best Regards, Dr. Amruta S. Dixit

We have a custom board with an STM32MP151A and STPMIC1. The PMIC is connected to I2C4 over pins PD12 and PD13.In the process of migrating our software from OpenSTLinux 6.0 to 6.2, I initially got stuck into an optee panic (attached optee-panic.log with optee log level set to 3); after some investigation I *think* I figured out that the problem was coming from I2C4 being assigned to the secure context, but pins D12/D13 not being secure.I managed to go around that by making the I2C4 controller non-secure and removing all reference to it from the optee dts, but then the kernel was hanging forever (attached optee-pass-kernel-fail.log) until I also marked the RCC as non-secure for optee and changed the clock definitions in the kernel to not use SCMI (to do so I had to patch stm32mp15-scmi.dtsi to be empty).I now have a booting configuration by essentially avoiding SCMI for clocks and regulators (I have attached the kernel and optee dts), but I am wondering whether this is necessary bec

I have an issue with PMIC. It seems that Op-tee won't start och activate the PMIC. Do you know why? Any suggestion? The error is 0xffff0008 = TEE_ERROR_ITEM_NOT_FOUND.Notice that I have copied the DT from DK board. F/TC:0 0 probe_driver_node:543 Probing stm32-gpu on node gpu@48280000 D/TC:0 0 probe_driver_node:556 element: stm32-gpu on node gpu@48280000 deferred 3 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32_pmic2 on node stpmic2@33 F/TC:0 0 stm32_pmic2_probe:923 Probe stpmic2 F/TC:0 0 initialize_pmic2:893 Initialize stpmic2 F/TC:0 0 lock_i2c_bus_access:796 thread access F/TC:0 0 unlock_i2c_bus_access:837 thread access completed F/TC:0 0 lock_i2c_bus_access:796 thread access F/TC:0 0 unlock_i2c_bus_access:837 thread access completed F/TC:0 0 stpmic2_register_read:259 REG[0 v=0x21 F/TC:0 0 lock_i2c_bus_access:796 thread access F/TC:0 0 unlock_i2c_bus_access:837 thread access completed F/TC:0 0 stpmic2_register_read:259 REG[0x1 v=0x11 I/TC: PMIC STPMIC REFID:2.A V1.1 F/TC:0

Hello,I am following AN4803 to simulate my board with an STM32MP151 with DDR3L memory, but there seems to be a problem with the IBIS model. These IBIS models have missing receiver voltage thresholds, which may affect analysis:IBIS File: C:\Users\...\IBIS\stm32mp151_153xaa_lfbga448_sm.ibsIBIS Model: MSD_D3RP3L_48Model does not have a [Receiver Thresholds] section.Only Vinh and Vinl thresholds are specified in the [Model Spec] section, and will be used for both AC and DC thresholds.Net: $9I75\DDR_DQ0Controller pin: U1.E21 (DDR_DQ0)Net: $9I75\DDR_DQ1Controller pin: U1.F21 (DDR_DQ1)Net: $9I75\DDR_DQ2Controller pin: U1.H21 (DDR_DQ2)Net: $9I75\DDR_DQ3Controller pin: U1.E20 (DDR_DQ3)Net: $9I75\DDR_DQ4Controller pin: U1.J21 (DDR_DQ4)Net: $9I75\DDR_DQ5Controller pin: U1.H20 (DDR_DQ5)Net: $9I75\DDR_DQ6Controller pin: U1.H22 (DDR_DQ6)Net: $9I75\DDR_DQ7Controller pin: U1.G19 (DDR_DQ7)Net: $9I75\DDR_DQ8Controller pin: U1.N22 (DDR_DQ8)Net: $9I75\DDR_DQ9Controller pin: U1.R21 (DDR_DQ9)Net: $9I75

I have a platform where I need two different Linux distros, one kinda like Android's recovery environment, and one main application environment.They will have different packages, and probably also different init-systems, as the recovery environment should be as small as possible, so I probably need to build them in separate steps and separate Yocto distros.Additionally the recovery environment will be completely stored in a separate NOR flash, where also the bootloader is stored, the main application distro will be in a NAND flash.How can I get the OpenSTLinux build system to generate an appropriate flashlayout for this?So far I got it to work with the bootloader in NOR and rootfs in NAND, but the extra system in NOR seems to be a bit more effort.

I am using the STM32MP131 in a baremetal environment. Since there is no internal flash, I am planning to use external flash and DDR.I have confirmed that writing to and reading from the flash works, but I don't know how to start from FLASH instead of SYSRAM when powering on.I saved the FW's bin data at address 0 of the Flash and tried changing the boot mode to QUADSPI Flash, but it did not work.I think QUADSPI needs to be activated before reading and executing from Flash. Where should I activate this?Do I also need to modify the linker script for the firmware that runs from Flash? Please let me know if you have any solutions to this problemThank you very much in advance.

Dear all, I was trying to setup the NVIC for EXTI for certain pins on STM32MP257F over CubeMX. However the nomenclature in CubeMX confuses me a lot. As I know there are two EXTIs: EXTI1 and EXTI2 which completely changes when we look into NVIC there it shows EXTI and EXTI1. Now the confusion is if EXTI is EXTI1 or 2 and so on.Thanking you all.with regardsAmit  

Hi,I’m working with a MYIR MYD-YA157C (STM32MP157AAC) board and I’m trying to restore a board using STM32CubeProgrammer (USB / DFU mode) with a FlashLayout TSV.The board is custom made , but the HW should not be a problemBut i am running into erorr: 16:47:55 : Download in Progress:16:47:56 : Error: failed to download Sector[0]16:47:56 : Error: failed to download the File16:47:56 : Error: Download partition 0x21 failed16:47:56 : Error: TSV flashing service failed16:47:56 : Disconnected from device. Little bit of a backgroundThe chip comes with preloaded yocto , and after trying to flash our distro we get this erorr  I tried the following thingsRemove everything from the EMMC - Nothing helpsChaning offsets - Did not helpUse UDF tool - Did not helpTried on different computer - Did not helpTried different cable  - Did not help It is very strange I attached logs from Cube programmer @Aimen1  Could somebody help us with some suggestions

I am working with the STM32MP257F-DK using the official Starter Package. Suddenly, the board entered a state where several power rails are disabled. The ST-LINK LED (LD5) is blinking red slowly, and there is no HDMI output (0V on the rail) I have SSH access via USB OTG (usb0), but the system is in a "degraded" state.The ST-LINK is not recognized by the PC.HDMI monitor detects no signal. Diagnostic Data (Output of grep "" /sys/class/regulator/*/state): I have attached a screenshot, but here are the critical regulators currently in disabled state:regulator.11 (vdd3v3_usb) -> disabledregulator.12 (v5v_hdmi) -> disabledregulator.3 (vddio3) & regulator.4 (vddio4) -> disabledregulator.7 (vddcore) -> disabled (Surprisingly, since the CPU is running).Attempts to fix: Tried to enable them via sysfs: echo enabled > /sys/class/regulator/regulator.12/state -> Result: Permission denied.Tried to force it via I2C: i2cset -f -y 0 0x33 0x93 0x01 -> Result: Write

经我这三两天的多次调试，我终于找到了问题所在先说segger rtt viewer的工作方式首先，我将segger rtt的源码编译烧录到stm32mp257d_m33那里去。这时m33核的暂存会持有一个_segger_rtt结构体。然后我将这个结构体地址提供给segger rtt viewer，这时就会成功建立起通讯现在我通过segger rtt viewer向stm32mp257d_m33发送数据，这时jlink这个硬件工具就会通过swd直接操作暂存将数据写入到_segger_rtt结构体的下行缓冲区，按理会同时更新_segger_rtt结构体下行缓冲区的写位置WrOff而我在stm32mp257d_m33的用户代码逻辑是，将从swd收到的数据即刻原封不动的发还回去下面是我实际使用segger rtt viewer时的输入输出窗口的内容00> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=0< 55600> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=0< 5645600> WrOff=557, RdOff=557, HasData=000> WrOff=557, RdOff=557, HasData=0< 546546500> WrOff=557, RdOff=5

gpioinfo outputgpiochip9 - 10 lines:line 0: "PZ0" inputline 1: "PZ1" inputline 2: "PZ2" inputline 3: "PZ3" inputgpiomon output# gpiomon --num-events 1 --edges falling PZ0^C# gpiomon --num-events 1 --edges falling PZ1^C# gpiomon --num-events 1 --edges falling PZ2^C# gpiomon --num-events 1 --edges falling PZ3gpiomon: unable to request lines on chip /dev/gpiochip9: No such device or addresswhy is there a problem with PZ3 pin specifically? noone is using itshould i add something in dts?

For the STM32MP135 series, specifically the STPMIC1A I'm using, can VDD_CORE and VDD_CPU share the same power rail (buck1)?

My device is quite power-sensitive. If I use a single DDR3L module with an STM32MP157 or 135, can I eliminate the need for a VTT power supply?

Dear ST Community,I am currently working on a custom hardware design based on the STM32MP157CAC3 MPU, which includes LPDDR3 memory (Micron MT52L256M32D1PF) and multiple high-speed interfaces.As part of my signal integrity and high-speed design validation process, I need simulation models to conduct accurate analysis.I want to request the following:IBIS models for STM32MP157CAC3, specifically covering:1. DDR interface (LPDDR2/LPDDR3 controller)2. SDMMC interface3. Any other relevant high-speed I/Os(MIPI, LTDC, DCMI, SDMMC)S-parameter models (if available) for:1. High-speed I/O buffers2. DDR interface pins or PHYAny additional resources that may support SI/PI analysis, such as:1. IBIS-AMI models (if available)2. Reference simulation setups3. Application notes related to DDR signal integrityProject details:Custom PCB (not a direct copy of STM32MP1 DK2)LPDDR3 operating btw 300 - 800 MHzGoal: Pre-layout and post-layout SI validation (HyperLynx/ADSI understand that some of these models may r

Hello! I'm attempting to build a custom bootloader for the STM32MP133C, heavily reliant upon the STM32MP13XX hal layer and then provided cmsis_core and cmsis_device_mp13 packages/pieces. I'm attempting this on IAR (company decision) which has added some wrinkles to this. I load the main application to the NAND flash using a custom flashloader, and then run the Bootloader code from sysram. Can't do both at the same time because IAR's flash loader uses the sysram.The bootloader initializes the necessary items- the HAL, system clock, DDR, UART, Flash, Ethernet, etc. I have it blink an LED 5 times for fun, and then load the .bin file from flash into a specific offset in the DDR, where I'm hoping to run from. I then set a function pointer to the starting location of the main app, and run that function pointer. It looks pretty simple/straightforward, as shown below:  GetApplicationDetails(flash); //loads from flash to DDR. void (*p_AppEntryPoint)(void);//boot the full OSp

I'm in a bit of a pickle. I got a MIPI DSI screen with 1200x1920 resolution. It turns out for SMT32MP25x max vertical supported resolution is 1536. But datasheet says this.  Some over-target non-guaranteed use cases are possible, but with specific constraints:• Drive simultaneously three panels, using the three interfaces (parallel, LVDS, DSI), witha same content.• Drive simultaneously two parallel LVDS panels, using each one link, with a reducedresolution and a same content.• Drive a 4 k panel via the DSI, with a limited features and performances: one layer,no resize, no rotation, 30 fps, and non-standardized blanking sizes. How do i specify those params in dts or/and linux panel driver? I tried setting 30Hz on panel, but that did not help - linux drm fails with "vblank wait timed out"This fails - 1200x1920@30Hz.clock = 80288,.hdisplay = 1200,.hsync_start = 1200 + 32,.hsync_end = 1200 + 32 + 14,.htotal = 1200 + 32 + 14 + 26,.vdisplay = 1920,.vsync_start = 1920

Is it okay to use the following connection for eMMC memory on the STM32MP157AAB3?Also, is it possible to set the eMMC memory to boot mode with this connection?PB14:SDMMC2_D0PB15:SDMMC2_D1PB3:SDMMC2_D2PB4:SDMMC2_D3PB8:SDMMC2_D4PB9:SDMMC2_D5PC6:SDMMC2_D6PC7:SDMMC2_D7PC1:SDMMC2_CKPG6:SDMMC2_CMD