PLL Settings

[qwer.asdf]

Posted on October 23, 2015 at 14:43

Hi, is there any difference how exactly I'm getting the desired clock speed on SYSCLK through PLL? For example, let's say I want to have 48MHz on SYSCLK on STM32F407, using a 8 MHz HSE and the PLL. One way of doing it would be this:

HSE = 8MHz

M = 8

 

N = 384

 

P = 8

 

Q = 8

 

--------

 

SYSCLK = 48MHz

Another way of doing it would this:

 

HSE = 8MHz

 

M = 4

 

N = 96

 

P = 4

 

Q = 4

 

--------

 

SYSCLK = 48MHz

So my question is: is one of these two ways better than the other (i.e. lower jitter, or lower power consumption), and why?

Thank you.

[waclawek.jan]

Posted on October 23, 2015 at 14:51

RM0090, rev.10 p.226, description of PLLM

Caution: The software has to set these bits correctly to ensure that the VCO input frequency

ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit

PLL jitter.

JW

[qwer.asdf]

Posted on October 23, 2015 at 15:00

Thanks, I missed it. So my second example is better because HSE/M = 2 opposed to HSE/M = 1 of the first example? And the N and P values don't affect the jitter?

[waclawek.jan]

Posted on October 23, 2015 at 15:33

This is all I know, I am not an ST insider. The ''2MHz causes less jitter'' is not quantified further either. The datasheet says, PLL input clock Typ 1MHz, which is confusing too.

OTOH, both N and P are purely digital dividers, whereas the PLL input frequency goes into the phase detector/feedback loop which is sort of analog, so I can imagine this is the case.

JW

[tm3341]

Posted on October 23, 2015 at 16:02

You also have to know that PLL_N must be at least 192 for proper working, according to the Reference manual.

These PLL combinations also needs to be set properly for other clock settings such as USB FS, LTDC, etc.

[qwer.asdf]

Posted on October 23, 2015 at 16:09

> You also have to know that PLL_N must be at least 192 for proper working, according to the Reference manual.

That's interesting, it means there is a bug in Cube's clock validation algorithms, because it doesn't mind if I set HSE=8,M=4,N=96,P=4,Q=4.

Edit:

Or maybe the 192MHz is for the output after the *N, that is (HSE / M) * N should be >=192 and <= 432. In my example it's (8 / 2) * 96 = 192, so it's valid.

Edit 2:

Nope, clearly Cube has a bug, it accepts even if I set HSE=8,M=4,N=50,P=4.

[waclawek.jan]

Posted on October 23, 2015 at 16:20

>You also have to know that PLL_N must be at least 192 for proper working, according to the Reference manual.

No, it was just a badly and confusingly formulated ''PLL VCO output frequency must be 192 to 432MHz, for the PLL input frequency of 1MHz it means N between 192 and 432''. Download and check out the latest Rev10 of RM0090.

JW

[waclawek.jan]

Posted on October 23, 2015 at 16:39

Cube, or CubeMX?

(Not that I would care.)

JW

[qwer.asdf]

Posted on October 23, 2015 at 16:44

You are right, it's STM32CubeMX.

[matic]

Posted on October 23, 2015 at 20:37

Is this true for all STM32 series?

[waclawek.jan]

Posted on October 23, 2015 at 22:54

Obviously no, and the PLLs in various sub-families differ significantly from each other - for example, while in 'F4 the PLL input clock range is 1-2MHz, in 'F1 this range is 1-25MHz.

JW