H743 480Mhz, VCO freq impossible?

[DOCon.1]

Does anyone know how you're supposed to get a clock speed of 480Mhz when the lowest PLLP1 divider is 2, and the max "wide" VCO freq (Input source / DIVM1 * DIVN1) is 836Mhz? Ie This seems to cap the max speed at 418Mhz. Of note, Cube doesn't complain about this setting, but my own validation code does, since the RM talks about this limit multiple times

This implies I'm misinterpreting the "F_VCO" from the RM, but it seems pretty explicit:

1: The software has to set correctly these bits to insure that the VCO output frequency is

between its valid frequency range, which is:

– 192 to 836 MHz if PLL1VCOSEL = ‘0’

...

2: VCO output frequency = Fref1_ck x DIVN1,

Ref_Ck appears to be the "PLL input frequency" of everything before PLLN. Ie the Input source, any scalers, and PLLM. How do you reconcile these? Thank you.

Summarized: It appears illegal to set PLL INPUT / DIVM * DIVN to be 960Mhz, which is required to get a sysclock of 480Mhz, because of the /2 PLLP minimum division.

[TDK]

I seem to recall the max VCO speed having conflicting information.

Yep, here it is. I suspect the real limit is 960 MHz. Or perhaps there really is a different limit for different chip revisions. Note this is for rev V hardware.

[DOCon.1]

I can confirm this from my User Manual. (The same you linked) Most likely explanation: The Reference Manual (RM0433, Rev 7 - the only H743 one linked on teh STM32H7 official page) is incorrect. It's listed as 836Mhz in Figure 47, and in 12 individual register-section config fields. 960 Mhz isn't mentioned anywhere.

[Uwe Bonnes]

I have 12110 Rev. 8 with PLL VCO Output listed as 960 MHz max

[Tesla DeLorean]

I had earlier X and Y step H7's running over 500 MHz, so the process has some pretty high ceiling

[DOCon.1]

Sweet. I'm unable to get past 400Mhz now due to a VOS error (It hangs while waiting for VOS0 to be ready), but that's probably due to a bug in my code. The initial problem was my own validation failing; I upped it to 960 based on the User manual, and annotated the RM0433 error. If any ST members are reading: This could be addressed in Rev 8.

[Amel NASRI]

Hi @DOCon.1​ ,

The same error was spotted in VCO frequency discrepancy in STM32H743 datasheet and reference manuals.

@Imen GH​  took already the action to raise an internal request for document update.

It is worth to make the update for figure 47 (PLL block diagram) in RM0433 as well. RM0399 has to be considered as well.

-Amel

[DOCon.1]

Thanks! I appreciate it.