differences between STM32H7 rev V and rev Y

[Mr_M_from_G]

Hello,

we use STM32H7 in our new development. I was excited about the announcement of the new revision V because it promises an increase of speed from 400MHz to 480 MHz. My distributor told me that except for that, the devices were hard- and software compatible.

Now I set a rev V STM32H742 into our prototype and after hours found out that there are a number of differences in ADC alone.

• So my first general question is, if there is a paper summarizing all the differences?
• My second question is, if the new ADC will in any case have at least the same performance as the old one (we use it at the edge of the old specs)?
• The third question is, when will a new package for CubeMX be available that support the new revision? I have STM32H7 package ver 1.2.0 and it complains when I try to set sysclk to 480 MHz.

Now some questions in detail:

• There is a new clk divider by two for adc_ker_clk. With the old settings for rev Y I get only half the samples per second. Can I simply double pll2_p_ck to get back to the old samples per second or are there limits in the ADC peripheral. (I tried it and it works but I need to be sure, that it is within specs)
• Datasheet of rev V gives for 14 bits resolution only 3.3 MSps which is too little for us. But it also says that this is with SMP = 2.5 while it is also possible to set SMP = 1.5, which is the value used in rev Y specs for all resolutions. Is there something wrong with using SMP = 1.5 with 14 bit resolution (or any other resolution) for rev V ?
• Is it still true, that fast channels are channels 0 .. 5 (RM0433 Rev 6 page 910)? Datasheet of STM32H742 says: (page 283) "4. Fast channels correspond to PC0, PC1, PC2, PC3, PA0, and PA1". We use PA6/7 = ADC1 INx3 and PC4/5 = ADC2 INx4 which would be fast for RM0433 but not for the datasheet.

I think we really need solutions for that because we can't stick to rev Y, it will not be produced anymore I guess (??)

So any help especially from ST members is greatly welcome

Thanks a lot

Martin

[Mr_M_from_G]

gently pushing this up again...

ST members, please can you give some information.

Thank you very much

Martin

[roland van straten]

I have some documents that explain the die change. One of them is AN5312 which describes the changes and ES0392 describing the errata. I received this some time ago from my distributer as I also use the H743.

You can find them through searching the ST.com website.

[Mr_M_from_G]

Roland,

thanks a lot for these hints, its a great help.

How did you set sysclk to 480 MHz? Simply increased DIVN1?

Martin

[roland van straten]

I have just generated a project with CubeMX and the H7 1.4.0 HAL Libraries.

I could set the appropriate parameters up to 480MHz for the H743. The clock window also shows the 480MHz max SYSCLK.

Generated a project for SW4STM32 as the tool generates an error if you select CubeIDE as target.

Did not check on actual hardware. You can easily extract the correct parameters to set for the clock from the generated code (as you probably know :-).

[Mr_M_from_G]

Thanks Roland,

I checked in CubeMX for updates of my H7 package but it showed none, my H7 package is 1.2.0. Maybe I also need the latest CubeMX version.

Which is your CubeMX version?

[Tesla DeLorean]

The 1.2.0 package is far too old to disclose any of the V step function and register bit level stuff. The current is 1.5.0

Higher speeds requires a different VOS settings and the PLL parameters tweaked.​

[roland van straten]

I have CubeMX 5.3.0...

[Mr_M_from_G]

Hello,

thanks for your answers.

Meanwhile I got the STM32H742 running with 480 MHz.

I installed CubeMX 5.3.0 and the H7 package 1.5.0.

Just to mention it, I had some trouble updating the old CubeMX and also could not run the installer from STs website. It showed a window with a CubeMX image for a second and then shutdown again. Finally I installed it via the command line DOS box as described in the CubeMX help.

Thanks again for your help

Martin

[Jack3]

A note on ADC between rev 'Y' and 'V'. I use the on-chip temperature sensor of the STM32H753ZIT. On rev Y, I got fairly stable readings, but on rev V, the reading were highly unstable. One of the major changes on the ADC interface is the clock scheme. With the addition of a divider by 2, Fadc_ker_ck for analog block is half the ADC input clock frequency. You may neeed to adjust ClockPrescaler and SamplingTime to make the reading stable again. Hope this helps.

[Rob vdH]

Hi,

I'm having the same problem. Needed a high sample rate/precision ADC. To my surprise I only got half of the expected sample rate. I could not figure out what was wrong until I saw that strange /2 clock divider in the reference manual.

For my project I minimally need an ADC doing 4 Msps/12 bit. For this I need to set fADC at 64 MHz (2*32) which CubeMX doesn't like (it automatically selects an ADC prescale factor of 2). I can override this in my code but I hesitate. I do not know what the maximum safe (not /2 divided) clock frequency of the ADC is. Can anyone shed some light on this?

Kind regards,

Rob.

[flyer31]

We use STM32H7 ADC with Y and V in somehow "compatible mode". As far as I remember, the main thing is that we HAVE to use the BOOST mode, then it worked with both versions nicely with identical settings (but no high-speed requirements in our application, and without "stupid CubeMX / HAL", just pure register programming).