ADC values are not stable in STM32H723ZG

[Arrhenius]

Hello everyone,

With respect to the Subject I am facing problem in reading analog voltage across the analog pins in the controller specified.

Following are the ADC configuration.

1. ADC resolution = 12Bit

2. Sclk = 256MHz

3. ADC clock source = Sclk/4

4. Prescaler = Div/1

5. Conversion data is stored in DR register

6. Conversion mode = single

7. Single ended mode 

8. Calibration is done in single endded mode

Note: GPIO is configured in Analog mode

Observation: The ADC value keeps on added up by 0 to 65 counts. The error keeps on changing dynamically in run time resulting in value instability. Due to which I am not able to provide the fixed offset values in OFRy registers.

I am also attaching the code snippet of the Init function. In the init function I am trying to configure ADC1,2 and 3.

Kindly have a look at it and provide me the solution.

Thanks in advance

Regards

Arrhenius

[Pavel A.]

Have you seen these threads?

https://community.st.com/s/question/0D53W00001TEY14SAH/h723zg-nucleo-adc-clocknoise-question

https://community.st.com/s/question/0D70X000007PAk8SAG/detail

[Andrew Neil]

@Arrhenius​ - "The ADC value keeps on added up by 0 to 65 counts"

Please could you clarify that?

Do you mean that it keeps monotonically increasing all the time? Or just that it varies each time by up to 65 counts from your "expected" value?

"The error keeps on changing dynamically in run time resulting in value instability"

The full range of your 12-bit ADC is 0-4095, so A count of 65 is just 1.6%

Are you sure that your input signal is actually that stable?

[Arrhenius]

Hi @Andrew Neil​ ,

First of all I thank you for responding to my query.

Q: Do you mean that it keeps monotonically increasing all the time? Or just that it varies each time by up to 65 counts from your "expected" value?

A: The value varies up to 65 counts. The error keeps changing dynamically in run time

The count 65 is nothing but, the adc ouput when the input is grounded(0v Nucleo board ground).

Our ADC accuracy requirement is less than 0.5%. We have a voltage divider circuit to read 200V. So, to read such a high value we expect the ADC shall have less error

For example: When 0v is fed to Ain, Ideally the count shall be 0. But we are reading value up to 65. So, for 0v input we read 0.0523V after multiplying with the resolution. On top of it we are Multiplying with the factor 83.5 which gives 4.37V for 0V for getting the value in 200V range..

Q: Are you sure that your input signal is actually that stable?

A: I believe that the ground 1.8v and 3.3v signals on Nucleo board are stable

[Andrew Neil]

The raw ADC result cannot possibly be any better than the accuracy/stability/precision of its analogue input signal.

So careful analogue design is critical.

Just "believing" that the supplies & ground are stable is not enough - you need to carefully check.

The Nucleo is a cheap, simple, general-purpose demo board - it isn't designed or optimised for precise analogue measurements. I'd say 1.6% is pretty good for such a board.

"We have a voltage divider circuit to read 200V"

you're going to need some pretty high-value resistors there - have you checked that the impedance is suitable to the ADC input?

ST has application notes for optimising ADC performance...

[Georgy Moshkin]

Sampling time is too short. You need to set SMPR register, currently it is probably 0 (1.5 cycles sampling time). Try something around 64.5 Cycles for testing