[LWIP] Rx buffers zero copy no MPU config

[Rado1]

HI

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Rx buffers labeled “Zero Copy” and are used by DMA and CPU are not marked by MPU for cacheable? 
only descriptors are.

 

I couldn’t find any special clean or flush cache operations in code as well.

 

Why is that?

 

Image below shows only descriptors (512B) and TX (LWIP heap) are noncacheable.

 

 

[SAHSTM]

Hello,

Thank you for your report,

The RX zero-copy buffers are not necessarily left cacheable without precautions; they are either placed in a memory region configured to avoid cache coherency issues, or cache coherency is handled by another part of the code. Descriptors are always treated separately because they are directly accessed by the DMA, whereas packet buffers follow a strategy specific to the LwIP/STM32H7 integration.

 

With Regards,

[lucas.meier55]

 

This is a good point about how the zero-copy RX buffers are handled. It sounds like the cacheability is intentional and managed by the LwIP/STM32H7 integration rather than requiring MPU configuration. The explanation about DMA access makes the behavior much clearer.