ST memory board configured for dual qspi on two octospi on STM32H5E5 Nucleo

[BMohl.1]

Hello,

I just purchased two STM32H5E5 Nucleo boards along with two of the ST Memory board kits. What I am planning is to take one of the QSPI flash M.2 boards and reconfigure it so that the memory(s) attached to OCTOSPI1 are two identical flash chips, and have two identical 64Mb PSRAMs attached to OCTOSPI2. Reading the octospi section of the reference manual it appears that each “bank” can share the clk and the OCTOSPI(1/2) chip selects and putting the respective OCTOSPI channels in DMM mode and have them memory mapped. Also, I have moved a SB on the Nucleo so that OCTOSPI2_NCS is connected to the M2.0 connector.  I have included a pic of what I am trying to do. Any help would be appreciated. 

 

Thank you,

 

[BMohl.1]

Actually, the way the M2.0 connector is routed has OCTOSP1 muxed with the possibility to tie octspi1_NCS2 into the second bank, not the octospi2 module. CAN the devices be memory mapped in this config?

[rich.g.williams]

I think yes, but it is all handled transparently (DMA) without any user setup and you never know any difference from as if it were on chip RAM.

[rich.g.williams]

I also have NUCLEO_H5E5ZJ boards and have drawn an unofficial schematic that might help you (its attached).  Also please have a look at my thread here:-NUCLEO_H5E5ZJ and selecting alternates using ST Core MX appreciate your comments.

I’m interested in exchanging any info on NUCLEO_H5E5ZJ and the STM32H5E5 MCU.

Richard

[Seb]

Most of the explanations and details are here : M.2/SerialMemory interface specification - Technical note

The add-on board replaces soldering, voltage regulation with enable control by MCU.

Your picture attachement is ok, simulating a dual octo (RAM+Flash) with two quad pairs.

The limitations and specifics resides on the base board available functionality.

Either there is a XSPI which has a single 8 bit data bus with dual chip select and share the same clock, or you have a dual XSPI with 8 bit data bus X1.D[0..7] &  X1.CLK/NCS , X2.D[0..7] & X2.CLK/NCS. So far, the second option is yet to be available (probably due to the number of pins required from the STM32 target package pincount.

In short, the baseboard defines/limit the available functionality and modularity of the serial memory add-on board.

[BMohl.1]

Seb, et al, thanks for the reply.

On doing a review of the Nucleo boards’ M2.0 A connector pinout I see that it has multiplexed Octspi 1 and Octopit 2s data lines together.  I have taken one of my memory pack boards and loaded it with two 4MB winbond flash and two SP-PSRAM64H 8MB psrams. the chips selects are as the pic I have posted. Using multiplexed dual quad SPI mode it now resembles this pic. The the clk and data lines are shared and I have configured the octoSPIM to be multiplexed both on OctospiM1s data lines. The flash is attached to OctoSPIM_NCS1 chip select and the PSRAM is connected to octoSPIM_NSC2. My question is in this multiplexed mode can the flash/PSRAM be memory mapped? If so, how do I go about doing that? Also, Since the SPI clock i shared can I changed the frequency if I want to clock either one faster/slower?

 

Thank you,

Brian

 

[Seb]

As said, check the reference manual of the corresponding STM32 for what the serial memory peripheral(s) can do. Each product is unique. Do check if you can share the same CLK for both OSPI_P1 and OSPI_P2 (serial interface IP names vary too, QSPI, OSPI, HSPI, XSPI….)

A quick refman read seems to show this :

 

STM32H5E4/5F4 and STM32H5E5/5F5 Arm<Sup>®</Sup>-based 32-bit MCUs - Reference manual